monitoring fpga firmware: Topics by WorldWideScience.org
FPGA programming using FX3

CERN Document Server

Calleja, Stefano

2014-01-01

An FPGA is required to be programmed via USB3 cable. Connectivity to the host PC is achieved by using an FX3 chip. By changing the firmware of the FX3, one can alter the function of the FX3. To program the FPGA via USB3, the FX3 must act as a connector from the host to the FPGA. This type of connection is known as an FPGA link. This method of connection is required to avoid programming the FPGA and FX3 dedicated memories and thus not having to use different programming methods and cables to program the board. It is considered that the FX3 is suitable to be used as an FPGA link since its previous version, the FX2, was also used as an FPGA link in a similar project. Firmware was downloaded on the FX3 using libusb and fx3load files from a Linux terminal. Some testing firmware was verified to perform as intended. However, the connection firmware intended to make the FPGA link truly functional has not been successful so far. Yet, through the FX3 documentation, it can be noted that an FPGA link is possible. UrJTAG ...

Evaluation of a feature extraction framework for FPGA firmware generation during a beam-test at CERN-SPS for the CBM-TRD experiment

Energy Technology Data Exchange (ETDEWEB)

Garcia Chavez, Cruz de Jesus; Munoz Castillo, Carlos Enrique; Kebschull, Udo [Infrastructure and Computer Systems in Data Processing (IRI), Goethe University, Frankfurt am Main (Germany); Collaboration: CBM-Collaboration

2016-07-01

A feature extraction framework has been developed to allow easy FPGA firmware generation for specific feature extraction algorithms in order to find and extract regions of interest within time-based signals. This framework allows the instantiation of multiple well-known feature extraction algorithms such as center of gravity, time over threshold and cluster finder, just to mention a few of them. A graphical user interface has also been built on top of the framework to provide a user-friendly way to visualize the data-flow architecture across processing stages. The FPGA platform constraints are automatically set up by the framework itself. This feature reduces the need of low-level hardware configuration knowledge that would normally be provided by the user, centering the attention in setting up the processing algorithms for the given task more than in writing hardware description code. During November 2015, a beam-test was performed at the CERN-SPS hall. The presented framework was used to generate a firmware for the SysCore3 FPGA development board used to readout two TRD detectors by means of the SPADIC 1.0 front-end chip. The framework architecture, design methodology, as well as the achieved results during the mentioned beam-test are presented.

FED firmware interface testing with pixel phase 1 emulator

CERN Document Server

Kilpatrick, Matthew

2017-01-01

A hardware emulation of the CMS pixel detector phase 1 upgrade front-end electronics has been developed to test and validate the architecture of the back-end electronics (FED) firmware. The emulation is implemented on a Virtex 6 FPGA on the CERN GLIB uTCA platform, utilizing an 8-way SFP FPGA Mezzanine Card to drive compatible optical transmitters to the back-end electronics at 400 bps. The firmware emulates the complex functions of the phase 1 pixel readout chips (PSI46digv2 and PROC600) and token bit manager ASICs and allows for possible abnormalities that can occur in the output data stream. The emulation implements both fixed data patterns that are used as test vectors and realistic simulated data to drive the readout of the FED at the expected data and trigger rates. Testing software was developed to control the emulator and verify correct transmission of data and exception handling in the FED. An installation has been integrated into the pixel DAQ test system at CMS to be used for fast validation of F...

FED firmware interface testing with pixel phase 1 emulator

CERN Document Server

Kilpatrick, Matthew

2018-01-01

A hardware emulation of the CMS pixel detector phase 1 upgrade front-end electronics has been developed to test and validate the architecture of the back-end electronics (FED) firmware. The emulation is implemented on a Virtex 6 FPGA on the CERN GLIB uTCA platform, utilizing an 8-way SFP FPGA Mezzanine Card to drive compatible optical transmitters to the back-end electronics at 400 bps. The firmware emulates the complex functions of the phase 1 pixel readout chips (PSI46digv2 and PROC600) and token bit manager ASICs and allows for possible abnormalities that can occur in the output data stream. The emulation implements both fixed data patterns that are used as test vectors and realistic simulated data to drive the readout of the FED at the expected data and trigger rates. Testing software was developed to control the emulator and verify correct transmission of data and exception handling in the FED. An installation has been integrated into the pixel DAQ test system at CMS to be used for fast validation of F...

Optimization on fixed low latency implementation of the GBT core in FPGA

Science.gov (United States)

Chen, K.; Chen, H.; Wu, W.; Xu, H.; Yao, L.

2017-07-01

In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [3]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [4, 5] is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

Optimization on fixed low latency implementation of the GBT core in FPGA

International Nuclear Information System (INIS)

Chen, K.; Chen, H.; Wu, W.; Xu, H.; Yao, L.

2017-01-01

In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [3]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [4, 5] is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

Wire scanner software and firmware issues

International Nuclear Information System (INIS)

Gilpatrick, John Doug

2008-01-01

The Los Alamos Neutron Science Center facility presently has 110 slow wire scanning profile measurement instruments located along its various beam lines. These wire scanners were developed and have been operating for at least 30 years. While the wire scanners solved many problems to operate and have served the facility well they have increasingly suffered from several problems or limitations, such as maintenance and reliability problems, antiquated components, slow data acquisition, and etc. In order to refurbish these devices, these wire scanners will be replaced with newer versions. The replacement will consist of a completely new beam line actuator, new cables, new electronics and brand new software and firmware. This note describes the functions and modes of operation that LabVIEW VI software on the real time controller and FPGA LabVIEW firmware will be required. It will be especially interesting to understand the overall architecture of these LabVIEW VIs. While this note will endeavor to describe all of the requirements and issues for the wire scanners, undoubtedly, there will be missing details that will be added as time progresses.

Histogramming in the LATOME-firmware for the Phase-1 upgrade of the ATLAS LAr calorimeter readout

Energy Technology Data Exchange (ETDEWEB)

Horn, Philipp; Hentges, Rainer; Straessner, Arno [Institut fuer Kern- und Teilchenphysik, Dresden (Germany)

2016-07-01

Due to the increased luminosity and the higher effective event rate after the phase 1 upgrade the ATLAS LAr detector needs new trigger electronics. The so-called LATOME-Board was designed as a LAr Digital Processing Blade (LPDB) to reconstruct the energy deposited by the particles and is an important part of the read out system. A prototype has already been build and the firmware for the on-board FPGA is under development. The insertion of a histogram-builder in this device gives the unique opportunity to look at untriggered data. This talk provides an insight in the LATOME-firmware and shows the different possibilities to implement the histogram-builder.

A low-power wave union TDC implemented in FPGA

International Nuclear Information System (INIS)

Wu, Jinyuan; Shi, Yanchen; Zhu, Douglas

2011-01-01

A low-power time-to-digital convertor (TDC) for an application inside a vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to reduce power consumption. The measurements indicate that with 32 channels fitting in the FPGA device, the power consumption on the FPGA core voltage is approximately 9.3 mW/channel and the total power consumption including both core and I/O banks is less than 27 mW/channel.

ALICE high-level trigger readout and FPGA processing in Run 2

Energy Technology Data Exchange (ETDEWEB)

Engel, Heiko; Kebschull, Udo [IRI, Goethe-Universitaet Frankfurt (Germany); Collaboration: ALICE-Collaboration

2016-07-01

The ALICE experiment uses the optical Detector Data Link (DDL) protocol to connect the detectors to the computing clusters of Data Acquisition (DAQ) and High-Level Trigger (HLT). The interfaces between the clusters and the optical links are realized with FPGA boards. HLT has replaced all of its interface boards with the Common Read-Out Receiver Card (C-RORC) for Run 2. This enables the read-out of detectors at higher link rates and allows to extend the data pre-processing capabilities, like online cluster finding, already in the FPGA. The C-RORC is integrated transparently into the existing HLT data transport framework and the cluster monitoring and management infrastructure. The board is in use since the start of LHC Run 2 and all ALICE data from and to HLT as well as all data from the TPC and the TRD is handled by C-RORCs. This contribution gives an overview on the firmware and software status of the C-RORC in the HLT.

Firmware implementation of algorithms for the new topological processor in the ATLAS first level trigger

Energy Technology Data Exchange (ETDEWEB)

Maldaner, Stephan; Caputo, Regina; Schaefer, Ulrich; Tapprogge, Stefan [Universitaet Mainz, Staudingerweg 7, 55128 Mainz (Germany)

2013-07-01

After the upgrade of the Large Hadron Collider in 2013/2014 proton-proton collisions will be provided at a center-of-mass energy of up to 14 TeV with an instantaneous luminosity of at least 1 . 10{sup 34} cm{sup -2}s{sup -1}. During this upgrade a new FPGA based electronics system (Topological Processor) will be included in the ATLAS trigger chain to keep up with the increased rate of events. To reduce rates while maintaining high signal efficiency of the trigger the processor will make its decisions based upon topological criteria like angular cuts and mass calculations. As a hardware based trigger, it will have to fit into the tight first level trigger latency budget of 2.5 Î¼s and thus provides the challenge of making decisions within very short time. Beside the latency, the main constraints on the algorithms are the required amount of logic resources of the FPGA which will be implemented as firmware. Therefore to be able to use as much information as possible, each module will be equipped with 2 state-of-the-art Xilinx Virtex 7 FPGAs to process the incoming data. This talk will present some of the topological algorithms and discuss properties of their implementation in firmware.

A firmware implementation of a Quad HOLA S-LINK to PCI Express interface for use in the ATLAS Trigger DAQ system

CERN Document Server

Slenders, Daniel

2014-01-01

The firmware for a PCI Express interface card with four on-board high-speed optical S-LINKS (FILAREXPRESS) has been developed. This was done for an Altera Stratix II GX FPGA. Furthermore, detection of the available channels through a pull-up resistor and a readout of the on-board temperature sensor were implemented.

An FPGA- Based General-Purpose Data Acquisition Controller

Science.gov (United States)

Robson, C. C. W.; Bousselham, A.; Bohm

2006-08-01

System development in advanced FPGAs allows considerable flexibility, both during development and in production use. A mixed firmware/software solution allows the developer to choose what shall be done in firmware or software, and to make that decision late in the process. However, this flexibility comes at the cost of increased complexity. We have designed a modular development framework to help to overcome these issues of increased complexity. This framework comprises a generic controller that can be adapted for different systems by simply changing the software or firmware parts. The controller can use both soft and hard processors, with or without an RTOS, based on the demands of the system to be developed. The resulting system uses the Internet for both control and data acquisition. In our studies we developed the embedded system in a Xilinx Virtex-II Pro FPGA, where we used both PowerPC and MicroBlaze cores, http, Java, and LabView for control and communication, together with the MicroC/OS-II and OSE operating systems

A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications

NARCIS (Netherlands)

Homulle, H.A.R.; Charbon, E.E.E.

2016-01-01

We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. This approach allows to alter the design, according to the system requirements, with simple modifications in the firmware. Therefore it can be used in a wide

FPGA-based trigger system for the Fermilab SeaQuest experimentz

Energy Technology Data Exchange (ETDEWEB)

Shiu, Shiuan-Hal, E-mail: shshiu@phys.sinica.edu.tw [Institute of Physics, Academia Sinica,128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan (China); Department of Physics, National Central University, No. 300, Jhongda Rd., Jhongli District, Taoyuan City 32001, Taiwan (China); Wu, Jinyuan [Fermi National Accelerator Laboratory, Kirk and Pine Streets, Batavia, IL 60510-5011 (United States); McClellan, Randall Evan [Department of Physics, University of Illinois at Urbana-Champaign, 1110 W. Green St., Urbana, IL 61801-3080 (United States); Chang, Ting-Hua; Chang, Wen-Chen; Chen, Yen-Chu [Institute of Physics, Academia Sinica,128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan (China); Gilman, Ron [Rutgers, The State University of New Jersey, 136 Frelinghuysen Rd., Piscataway, NJ 08854 (United States); Nakano, Kenichi [Department of Physics, Tokyo Institute of Technology, 2-12-1 Ookayama, Meguro-ku, Tokyo 152-8550 (Japan); Peng, Jen-Chieh [Department of Physics, University of Illinois at Urbana-Champaign, 1110 W. Green St., Urbana, IL 61801-3080 (United States); Wang, Su-Yin [Institute of Physics, Academia Sinica,128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan (China); Fermi National Accelerator Laboratory, Kirk and Pine Streets, Batavia, IL 60510-5011 (United States); Department of Physics, National Kaohsiung Normal University, No. 62, Shenjhong Rd.,Yanchao Township, Kaohsiung County 824, Taiwan (China)

2015-12-01

The SeaQuest experiment (Fermilab E906) detects pairs of energetic Î¼{sup +} and Î¼{sup â} produced in 120 GeV/c protonânucleon interactions in a high rate environment. The trigger system consists of several arrays of scintillator hodoscopes and a set of field-programmable gate array (FPGA) based VMEbus modules. Signals from up to 96 channels of hodoscope are digitized by each FPGA with a 1-ns resolution using the time-to-digital convertor (TDC) firmware. The delay of the TDC output can be adjusted channel-by-channel in 1-ns step and then re-aligned with the beam RF clock. The hit pattern on the hodoscope planes is then examined against pre-determined trigger matrices to identify candidate muon tracks. Information on the candidate tracks is sent to the 2nd-level FPGA-based track correlator to find candidate di-muon events. The design and implementation of the FPGA-based trigger system for SeaQuest experiment are presented.

Firmware-only implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA)

International Nuclear Information System (INIS)

Jinyuan Wu; Zonghan Shi; Irena Y Wang

2003-01-01

A Time-to-Digital Converter (TDC) implemented in general purpose field-programmable gate array (FPGA) for the Fermilab CKM experiment will be presented. The TDC uses a delay chain and register array structure to produce lower bits in addition to higher bits from a clock counter. Lacking the direct controls custom chips, the FPGA implementation of the delay chain and register array structure had to address two major problems: (1) the logic elements used for the delay chain and register array structure must be placed and routed by the FPGA compiler in a predictable manner, to assure uniformity of the TDC binning and short-term stability. (2) The delay variation due to temperature and power supply voltage must be compensated for to assure long-term stability. They used the chain structures in the existing FPGAs that the venders designed for general purpose such as carry algorithm or logic expansion to solve the first problem. To compensate for delay variations, they studied several digital compensation strategies that can be implemented in the same FPGA device. Some bench-top test results will also be presented in this document

FPGA implementation of a hybrid on-line process monitoring in PC based real-time systems

Directory of Open Access Journals (Sweden)

JovanoviÄ Bojan

2011-01-01

Full Text Available This paper presents one way of FPGA implementation of hybrid (hardware-software based on-line process monitoring in Real-Time systems (RTS. The reasons for RTS monitoring are presented at the beginning. The summary of different RTS monitoring approaches along with its advantages and drawbacks are also exposed. Finally, monitoring module is described in details. Also, FPGA implementation results and some useful monitoring system applications are mentioned.

The new FPGA based discriminator board for the CBELSA/TAPS experiment

Energy Technology Data Exchange (ETDEWEB)

Fix, Eugenia [HISKP, Universitaet Bonn (Germany); Collaboration: CBELSA/TAPS-Collaboration

2016-07-01

The Crystal Barrel calorimeter at ELSA, which consists of 1320 CsI(Tl) crystals has been upgraded by a new Avalanche Photo Diode (APD) crystal readout.The APD readout electronics will provide a fast trigger signal down to 10 MeV energy deposit per single crystal. The processing of these trigger signals requires the development of a previously not existent timing branch of the readout chain of the Crystal Barrel calorimeter. Core component of the timing branch is a newly developed, FPGA based discriminator board. Its firmware contains modules for time to digital conversion, rise time compensation and parts of a cluster finder. In addition the reference voltages and discriminator thresholds are controlled and monitored. This poster presents the design and the achievable accuracy of the new discriminator.

LHCb: Radiation tolerance tests of SRAM-based FPGAs for the possible usage in the readout electronics for the LHCb experiment

CERN Multimedia

Faerber, C; Wiedner, D; Leveringzon, B; Ekelhof, R

2013-01-01

This paper describes radiation studies of SRAM-based FPGAs as a central component of the electronics for a possible upgrade of the LHCb Outer Tracker readout electronics to a frequency of 40 MHz. Two Arria GX FPGAs were irradiated with 20 MeV protons to radiation doses of up to 7 Mrad. During and between the irradiation periods the different FPGA currents, the package temperature, the firmware error rate, the PLL stability, and the stability of a 32 channel TDC implemented on the FPGA were monitored. Results on the radiation tolerance of the FPGA and the measured firmware error rates will be presented. The Arria GX FPGA fulfils the radiation tolerance required for the LHCb upgrade (30 krad) and an expected firmware error rate of 10$^{-6}$ Hz makes the chip viable for the LHCb Upgrade.

FPGA Implementation of Heart Rate Monitoring System.

Science.gov (United States)

Panigrahy, D; Rakshit, M; Sahu, P K

2016-03-01

This paper describes a field programmable gate array (FPGA) implementation of a system that calculates the heart rate from Electrocardiogram (ECG) signal. After heart rate calculation, tachycardia, bradycardia or normal heart rate can easily be detected. ECG is a diagnosis tool routinely used to access the electrical activities and muscular function of the heart. Heart rate is calculated by detecting the R peaks from the ECG signal. To provide a portable and the continuous heart rate monitoring system for patients using ECG, needs a dedicated hardware. FPGA provides easy testability, allows faster implementation and verification option for implementing a new design. We have proposed a five-stage based methodology by using basic VHDL blocks like addition, multiplication and data conversion (real to the fixed point and vice-versa). Our proposed heart rate calculation (R-peak detection) method has been validated, using 48 first channel ECG records of the MIT-BIH arrhythmia database. It shows an accuracy of 99.84%, the sensitivity of 99.94% and the positive predictive value of 99.89%. Our proposed method outperforms other well-known methods in case of pathological ECG signals and successfully implemented in FPGA.

Development of Î³ dose rate monitor based on FPGA and single-chip microcomputer

International Nuclear Information System (INIS)

He Zhiguo; Ling Qiu; Guo Lanying; Yang Binhua

2009-01-01

A novelÎ³dose rate monitor with multiple channels signal collection in which takes the FPGA as the core process chip and single-chip microcomputer as the data processor had been developed. This paper introduced the communication interface design between FPGA and MCU, and gave the data acquisition module and the function simulation chart designed by FPGA. In addition, the software and hardware design diagrams of MCU had been given in this paper. The maximum digitallization was carried on in the designing process. The experiments showed that the scheme for the system matched to the requests completely. (authors)

FPGA-based prototype of portable environmental radiation monitor

Energy Technology Data Exchange (ETDEWEB)

Benahmed, A.; Elkarch, H. [CNESTEN -Centre National de l' Energie des Sciences et Techniques Nucleaires (Morocco)

2015-07-01

This new portable radiological environmental monitor consists of 2 main components, Gamma ionization chamber and a FPGA-based electronic enclosure linked to convivial software for treatment and analyzing. The HPIC ion chamber is the heart of this radiation measurement system and is running in range from 0 to 100 mR/h, so that the sensitivity at the output is 20 mV/Î¼R/h, with a nearly flat energy response from 0,07 to 10 MEV. This paper presents a contribution for developing a new nuclear measurement data acquisition system based on Cyclone III FPGA Starter Kit ALTERA, and a user-friendly software to run real-time control and data processing. It was developed to substitute the older radiation monitor RSS-112 PIC installed in CNESTEN's Laboratory in order to improve some of its functionalities related to acquisition time and data memory capacity. As for the associated acquisition software, it was conceived under the virtual LabView platform from National Instrument, and offers a variety of system setup for radiation environmental monitoring. It gives choice to display both the statistical data and the dose rate. Statistical data shows a summary of current data, current time/date and dose integrator values, and the dose rate displays the current dose rate in large numbers for viewing from a distance as well as the date and time. The prototype version of this new instrument and its data processing software has been successfully tested and validated for viewing and monitoring the environmental radiation of Moroccan nuclear center. (authors)

Nd:YAG Laser Firmware Design under RTOS Operation

Energy Technology Data Exchange (ETDEWEB)

Kim, B. G.; Kim, W. Y.; Park, G. R.; Moon, D. S.; Hong, J. H.; Kim, H. J.; Cho, J. S. [Pusan National University (Korea)

2000-07-01

A pulsed Nd:YAG laser is used widely for materials processing and medical instrument. It's very important to control the laser energy density in those fields using a pulsed Nd:YAG laser. A pulse repetition rate and a pulse width are regarded as the most dominant factors to control the energy density of laser beam. In this paper, the alternating charge and discharge system was designed to adjust a pulse repetition rate. This system is controlled by microprocessor and allows to replace an expensive condenser for high frequency to cheap one of low frequency. In addition, The microcontroller monitors the flow of cooling water, short circuit, and miss firing and so on. We designed Nd:YAG laser firmware with smart microcontroller, and want to explain general matters about the firmware from now. (author). 8 refs., 6 figs.

Development of an FPGA-based multipoint laser pyroshock measurement system for explosive bolts

International Nuclear Information System (INIS)

Abbas, Syed Haider; Lee, Jung-Ryul; Jang, Jae-Kyeong; Kim, Zaeill

2016-01-01

Pyroshock can cause failure to the objective of an aerospace structure by damaging its sensitive electronic equipment, which is responsible for performing decisive operations. A pyroshock is the high intensity shock wave that is generated when a pyrotechnic device is explosively triggered to separate, release, or activate structural subsystems of an aerospace architecture. Pyroshock measurement plays an important role in experimental simulations to understand the characteristics of pyroshock on the host structure. This paper presents a technology to measure a pyroshock wave at multiple points using laser Doppler vibrometers (LDVs). These LDVs detect the pyroshock wave generated due to an explosive-based pyrotechnical event. Field programmable gate array (FPGA) based data acquisition is used in the study to acquire pyroshock signals simultaneously from multiple channels. This paper describes the complete system design for multipoint pyroshock measurement. The firmware architecture for the implementation of multichannel data acquisition on an FPGA-based development board is also discussed. An experiment using explosive bolts was configured to test the reliability of the system. Pyroshock was generated using explosive excitation on a 22-mm-thick steel plate. Three LDVs were deployed to capture the pyroshock wave at different points. The pyroshocks captured were displayed as acceleration plots. The results showed that our system effectively captured the pyroshock wave with a peak-to-peak magnitude of 303 741 g. The contribution of this paper is a specialized architecture of firmware design programmed in FPGA for data acquisition of large amount of multichannel pyroshock data. The advantages of the developed system are the near-field, multipoint, non-contact, and remote measurement of a pyroshock wave, which is dangerous and expensive to produce in aerospace pyrotechnic tests.

Development of an FPGA-based multipoint laser pyroshock measurement system for explosive bolts

Energy Technology Data Exchange (ETDEWEB)

Abbas, Syed Haider; Lee, Jung-Ryul [Department of Aerospace Engineering, Korea Advanced Institute of Science and Technology, Daejeon (Korea, Republic of); Jang, Jae-Kyeong [The Engineering Institute-Korea, Chonbuk National University, Jeonju (Korea, Republic of); Kim, Zaeill [The 4th R& D Institute-1st directorate, Agency for Defense Development, Daejeon (Korea, Republic of)

2016-07-15

Pyroshock can cause failure to the objective of an aerospace structure by damaging its sensitive electronic equipment, which is responsible for performing decisive operations. A pyroshock is the high intensity shock wave that is generated when a pyrotechnic device is explosively triggered to separate, release, or activate structural subsystems of an aerospace architecture. Pyroshock measurement plays an important role in experimental simulations to understand the characteristics of pyroshock on the host structure. This paper presents a technology to measure a pyroshock wave at multiple points using laser Doppler vibrometers (LDVs). These LDVs detect the pyroshock wave generated due to an explosive-based pyrotechnical event. Field programmable gate array (FPGA) based data acquisition is used in the study to acquire pyroshock signals simultaneously from multiple channels. This paper describes the complete system design for multipoint pyroshock measurement. The firmware architecture for the implementation of multichannel data acquisition on an FPGA-based development board is also discussed. An experiment using explosive bolts was configured to test the reliability of the system. Pyroshock was generated using explosive excitation on a 22-mm-thick steel plate. Three LDVs were deployed to capture the pyroshock wave at different points. The pyroshocks captured were displayed as acceleration plots. The results showed that our system effectively captured the pyroshock wave with a peak-to-peak magnitude of 303 741 g. The contribution of this paper is a specialized architecture of firmware design programmed in FPGA for data acquisition of large amount of multichannel pyroshock data. The advantages of the developed system are the near-field, multipoint, non-contact, and remote measurement of a pyroshock wave, which is dangerous and expensive to produce in aerospace pyrotechnic tests.

FE-I4 Firmware Development and Integration with FELIX for the Pixel Detector

CERN Document Server

Yadav, Amitabh; Sharma, Abhishek; CERN. Geneva. EP Department

2017-01-01

CERN has planned a series of upgrades for the LHC. The last in this current series of planned upgrades is designated the HL-LHC. At the same time, the ATLAS Experiment will be extensively changed to meet the challenges of this upgrade (termed as the âPhase-IIâ upgrade). The Inner Detector will be completely rebuilt for the phase-II. The TRT, SCT and Pixel will be replaced by the all-silicon tracker, termed as the Inner Tracker (ITk). The read-out of this future ITk detector is an engineering challenge for the routing of services and quality of the data. This document describes the FPGA firmware development that integrates the GBT, Elink and Rx-Tx Cores for communication between the FE-I4 modules and the FELIX read-out system.

Wire Position Monitoring with FPGA based Electronics

International Nuclear Information System (INIS)

Eddy, N.; Lysenko, O.

2009-01-01

This fall the first Tesla-style cryomodule cooldown test is being performed at Fermilab. Instrumentation department is preparing the electronics to handle the data from a set of wire position monitors (WPMs). For simulation purposes a prototype pipe with a WMP has been developed and built. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The wire is stretched along the pipe with a tensioning load of 9.07 kg. The WPM consists of four 50 (Omega) striplines spaced 90 o apart. FPGA based digitizer scans the WPM and transmits the data to a PC via VME interface. The data acquisition is based on the PC running LabView. In order to increase the accuracy and convenience of the measurements some modifications were required. The first is implementation of an average and decimation filter algorithm in the integrator operation in the FPGA. The second is the development of alternative tool for WPM measurements in the PC. The paper describes how these modifications were performed and test results of a new design. The last cryomodule generation has a single chain of seven WPMs (placed in critical positions: at each end, at the three posts and between the posts) to monitor a cold mass displacement during cooldown. The system was developed in Italy in collaboration with DESY. Similar developments have taken place at Fermilab in the frame of cryomodules construction for SCRF research. This fall preliminary cryomodule cooldown test is being performed. In order to prepare an appropriate electronic system for the test a prototype pipe with a WMP has been developed and built, figure 1. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The 0.5 mm diameter Cu wire is stretched along the pipe with a tensioning load of 9.07 kg and has a length of 1.1 m. The WPM consists of four 50 (Omega) striplines spaced 90 o apart. An FPGA based digitizer

A novel FPGA-based bunch purity monitor system at the APS storage ring

International Nuclear Information System (INIS)

Norum, W.E.

2008-01-01

Bunch purity is an important source quality factor for the magnetic resonance experiments at the Advanced Photon Source. Conventional bunch-purity monitors utilizing time-to-amplitude converters are subject to dead time. We present a novel design based on a single field- programmable gate array (FPGA) that continuously processes pulses at the full speed of the detector and front-end electronics. The FPGA provides 7778 single-channel analyzers (six per rf bucket). The starting time and width of each single-channel analyzer window can be set to a resolution of 178 ps. A detector pulse arriving inside the window of a single-channel analyzer is recorded in an associated 32-bit counter. The analyzer makes no contribution to the system dead time. Two channels for each rf bucket count pulses originating from the electrons in the bucket. The other four channels on the early and late side of the bucket provide estimates of the background. A single-chip microcontroller attached to the FPGA acts as an EPICS IOC to make the information in the FPGA available to the EPICS clients.

Optimizing latency in Xilinx FPGA implementations of the GBT

CERN Document Server

Muschter, S; Bohm, C; Cachemiche, J-P; Baron, S

2010-01-01

The GigaBit Transceiver (GBT) {[}1] system has been developed to replace the Timing, Trigger and Control (TTC) system {[}2], currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation {[}3]. This code was optimized for resource utilization {[}4], as the GBT protocol is very demanding. It was not, however, optimized for latency - which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The la...

Firmware development for VMM testing

CERN Document Server

Amayuelas Fernandez, Alfonso

2017-01-01

The collaboration has been carried out within the ATLAS Detector Systems area, in the Electronics Department for the muon spectrometer. This includes the team from the National Technical University of Athens (NTUA). The project involves the firmware development of the FPGAs for the configuration of the readout chip used in the detector (known as VMM). Some changes in the firmware were needed in order to check the configuration was correctly sent and the chip configured. The aim of this report is to describe the project in detail, how it has been developed and which problems have been encountered during the process.

A FPGA Embedded Web Server for Remote Monitoring and Control of Smart Sensors Networks

Science.gov (United States)

Magdaleno, Eduardo; RodrÃ­guez, Manuel; PÃ©rez, Fernando; HernÃ¡ndez, David; GarcÃ­a, Enrique

2014-01-01

This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the Î¼CLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI). The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A). Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology. PMID:24379047

A FPGA embedded web server for remote monitoring and control of smart sensors networks.

Science.gov (United States)

Magdaleno, Eduardo; RodrÃ­guez, Manuel; PÃ©rez, Fernando; HernÃ¡ndez, David; GarcÃ­a, Enrique

2013-12-27

This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the Î¼CLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI). The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A). Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology.

A FPGA Embedded Web Server for Remote Monitoring and Control of Smart Sensors Networks

Directory of Open Access Journals (Sweden)

Eduardo Magdaleno

2013-12-01

Full Text Available This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the Î¼CLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI. The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A. Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology.

FPGA-based calibration and monitoring system for the HADES electromagnetic calorimeter

Energy Technology Data Exchange (ETDEWEB)

Lai, Alessandra [University of Turin (Italy); GSI Helmholtzzentrum fuer Schwerionenforschung, Darmstadt (Germany); Collaboration: HADES-Collaboration

2015-07-01

The High Acceptance Di-Electron Spectrometer (HADES) at GSI was designed to measure dileptons and strangeness in elementary and heavy-ion collisions. An upgrade of HADES with an Electromagnetic Calorimeter (ECAL) has started and will be ready for beam in 2017. The goal is to measure Ï{sup 0} and Î· meson yields together with the dielectron data in pion and proton-induced reactions as well as in heavy ion collisions. Moreover, photon measurement is important for Î{sup 0} (1405) and Î£{sup 0} (1385) spectroscopy. It is essential to precisely calibrate all the lead-glass crystal modules individually in order to achieve the required ECAL performances. Continuous monitoring with a light pulser system is required. It is foreseen to use blue light from an LED source, driven by short signals from a flexible pulse generator and distributed with optical fibers to each module of the ECAL. Due to their great flexibility, Field Programmable Gate Arrays (FPGA) have been chosen to implement the mentioned monitoring system. In this contribution an FPGA-based calibration system for commissioning as well as long term stability of the ECAL modules are presented.

Michael Niegl (1985-2009)

CERN Multimedia

2009-01-01

Our friend and colleague Michael Niegl died in a tragic accident in the first hours of the new year. Michael was a Masterâs student in Microsystems Engineering at the University of Applied Sciences Wiener Neustadt. He was responsible for the development of the ATLAS Beam Conditions Monitor (BCM) ROD FPGA firmware, which acquires the data from the BCM detector modules and provides online monitoring of the LHC beams within the ATLAS experiment. He spent several months at CERN to carry out beam tests on the BCM detectors and received his Bachelor of Science with first class honours for his thesis: Concept and Implementation of an FPGA-based Data Recorder and Processor for the ATLAS Beam Conditions Monitor. Michael spent six months at CERN last year to finish the development and commissioning of the ROD firmware for the first beam. He worked the entire night of 10 September to fine tune the system for the first beam. It was a joy to ...

Remote monitoring and fault recovery for FPGA-based field controllers of telescope and instruments

Science.gov (United States)

Zhu, Yuhua; Zhu, Dan; Wang, Jianing

2012-09-01

As the increasing size and more and more functions, modern telescopes have widely used the control architecture, i.e. central control unit plus field controller. FPGA-based field controller has the advantages of field programmable, which provide a great convenience for modifying software and hardware of control system. It also gives a good platform for implementation of the new control scheme. Because of multi-controlled nodes and poor working environment in scattered locations, reliability and stability of the field controller should be fully concerned. This paper mainly describes how we use the FPGA-based field controller and Ethernet remote to construct monitoring system with multi-nodes. When failure appearing, the new FPGA chip does self-recovery first in accordance with prerecovery strategies. In case of accident, remote reconstruction for the field controller can be done through network intervention if the chip is not being restored. This paper also introduces the network remote reconstruction solutions of controller, the system structure and transport protocol as well as the implementation methods. The idea of hardware and software design is given based on the FPGA. After actual operation on the large telescopes, desired results have been achieved. The improvement increases system reliability and reduces workload of maintenance, showing good application and popularization.

FPGA based compute nodes for high level triggering in PANDA

International Nuclear Information System (INIS)

Kuehn, W; Gilardi, C; Kirschner, D; Lang, J; Lange, S; Liu, M; Perez, T; Yang, S; Schmitt, L; Jin, D; Li, L; Liu, Z; Lu, Y; Wang, Q; Wei, S; Xu, H; Zhao, D; Korcyl, K; Otwinowski, J T; Salabura, P

2008-01-01

PANDA is a new universal detector for antiproton physics at the HESR facility at FAIR/GSI. The PANDA data acquisition system has to handle interaction rates of the order of 10 7 /s and data rates of several 100 Gb/s. FPGA based compute nodes with multi-Gb/s bandwidth capability using the ATCA architecture are designed to handle tasks such as event building, feature extraction and high level trigger processing. Data connectivity is provided via optical links as well as multiple Gb Ethernet ports. The boards will support trigger algorithms such us pattern recognition for RICH detectors, EM shower analysis, fast tracking algorithms and global event characterization. Besides VHDL, high level C-like hardware description languages will be considered to implement the firmware

Implementing Temperature Supervision for the ALICE CRU Card Using the Onboard Microcontroller

CERN Document Server

Perez Bernabeu, Ruben

2017-01-01

We report on the first implementation of the thermal supervisory firmware for the onboard microcontroller on the ALICE CRU card. The Common Readout Unit (CRU) is a custom PCI Express FPGA card developed by âCentre Physique des Particules de Marseilleâ in collaboration of LHCb and ALICE. While the main effort has been focused on the development of the FPGA firmware that implements all the communication needs, there are several independent design tasks identified to ensure the safe operation of the CRU card under all possible conditions. One such task is to implement a robust local (on-board) temperature monitoring and safeguarding subsystem based on ATmega128 microcontroller. It will autonomously prevent the thermal damage of the card even if the remote HW monitoring and controlling functions (integrated in DCS) failed for any reason. Consequently, our main goal in this project will be implementing the temperature supervision using the onboard microcontroller.

Sustainable and Practical Firmware Upgrade for Wireless Access Point Using Password-Based Authentication

Directory of Open Access Journals (Sweden)

Jaejin Jang

2016-08-01

Full Text Available Wireless access points (WAPs are devices that provide Internet connectivity to devices such as desktops, laptops, smartphones, and tablets. Hence, it is important to provide sufficient availability to devices and security for the traffic that is routed by a WAP. However, attackers can decrease the network bandwidth or obtain the traffic including private data such as search histories, login information, and device usage patterns by exploiting the vulnerabilities in firmware upgrades to install malicious firmware. To address this problem, we propose a sustainable and practical firmware upgrade for a WAP using password-based authentication. The proposed upgrade protocol ensures security by adding freshness to the firmware whenever a firmware upgrade occurs. This freshness is different for each event and each firmware; therefore, even if the freshness of one firmware is exposed, the others are secure. In addition, confidentiality, integrity, and authentication are ensured. Furthermore, the proposed protocol can be easily implemented and adapted to WAPs. Experiments are performed to evaluate the upgrade time, resource usage, and code size in wired and wireless connected environments by implementing a prototype and analyzing the security of the protocol. The results show that the proposed upgrade is secure and practical.

Software/firmware design specification for 10-MWe solar-thermal central-receiver pilot plant

Energy Technology Data Exchange (ETDEWEB)

Ladewig, T.D.

1981-03-01

The software and firmware employed for the operation of the Barstow Solar Pilot Plant are completely described. The systems allow operator control of up to 2048 heliostats, and include the capability of operator-commanded control, graphic displays, status displays, alarm generation, system redundancy, and interfaces to the Operational Control System, the Data Acquisition System, and the Beam Characterization System. The requirements are decomposed into eleven software modules for execution in the Heliostat Array Controller computer, one firmware module for execution in the Heliostat Field Controller microprocessor, and one firmware module for execution in the Heliostat Controller microprocessor. The design of the modules to satisfy requirements, the interfaces between the computers, the software system structure, and the computers in which the software and firmware will execute are detailed. The testing sequence for validation of the software/firmware is described. (LEW)

An FPGA based backup version of the TileCal digitizer

International Nuclear Information System (INIS)

Eriksson, D; Muschter, S; Bohm, C

2010-01-01

The ATLAS Tile Calorimeter front end digitization and readout system comprises about 1800 digitizer boards with two TileDMU ASICs on each board. The TileDMUs are responsible for storing, derandomising and reading out digitized data from twelve ADCs. An ample number of board spares are available. However, a backup solution is desirable in the event of unexpected failure modes. The original version contains both outdated and custom made circuits that are difficult or impossible to find in sufficient numbers. We have developed a new version using inexpensive off the shelf FPGAs (Spartan 6). The FPGAs have all the necessary functionality to emulate the TileDMU and will be readily available for a considerable time. The new board is functionally compatible with the current version and to a large extent uses the same code. The design goal was to leave the digitizer design as intact as possible since it is well tested and performs well. As radiation tolerance is an issue we have implemented triple mode redundancy in the FPGA. To further improve the system we added in system programmability via TTCrx for both the FPGA and the configuration memory using one way JTAG. This provides a way to recover from radiation damage to the configuration PROM or to remotely upgrade system firmware.

An FPGA based backup version of the TileCal digitizer.

Science.gov (United States)

Eriksson, D.; Muschter, S.; Bohm, C.

2010-11-01

The ATLAS Tile Calorimeter front end digitization and readout system comprises about 1800 digitizer boards with two TileDMU ASICs on each board. The TileDMUs are responsible for storing, derandomising and reading out digitized data from twelve ADCs. An ample number of board spares are available. However, a backup solution is desirable in the event of unexpected failure modes. The original version contains both outdated and custom made circuits that are difficult or impossible to find in sufficient numbers. We have developed a new version using inexpensive off the shelf FPGAs (Spartan 6). The FPGAs have all the necessary functionality to emulate the TileDMU and will be readily available for a considerable time. The new board is functionally compatible with the current version and to a large extent uses the same code. The design goal was to leave the digitizer design as intact as possible since it is well tested and performs well. As radiation tolerance is an issue we have implemented triple mode redundancy in the FPGA. To further improve the system we added in system programmability via TTCrx for both the FPGA and the configuration memory using one way JTAG. This provides a way to recover from radiation damage to the configuration PROM or to remotely upgrade system firmware.

Optimizing latency in Xilinx FPGA implementations of the GBT

International Nuclear Information System (INIS)

Muschter, S; Bohm, C; Baron, S; Soos, C; Cachemiche, J-P

2010-01-01

The GigaBit Transceiver (GBT) system has been developed to replace the Timing, Trigger and Control (TTC) system, currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation. This code was optimized for resource utilization, as the GBT protocol is very demanding. It was not, however, optimized for latency - which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The latency optimization results were compared with measurement results from a Virtex 6 ML605 development board equipped with a XC6VLX240T with speedgrade-1 and the package FF1156. Bit error rate tests were also performed to ensure an error free operation. The two final optimizations were analyzed for utilization and compared with the original code, distributed in the Starter Kit.

Firmware development and testing of the ATLAS Pixel Detector / IBL ROD card

International Nuclear Information System (INIS)

Gabrielli, A.; Balbi, G.; Falchieri, D.; Lama, L.; Travaglini, R.; Backhaus, M.; Bindi, M.; Chen, S.P.; Hauck, S.; Hsu, S.C.; Flick, T.; Wensing, M.; Kretz, M.; Kugel, A.

2015-01-01

The ATLAS Experiment is reworking and upgrading systems during the current LHC shut down. In particular, the Pixel detector has inserted an additional inner layer called the Insertable B-Layer (IBL). The Readout-Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBL's off-detector DAQ system. The strategy for IBL ROD firmware development was three-fold: keeping as much of the Pixel ROD datapath firmware logic as possible, employing a complete new scheme of steering and calibration firmware, and designing the overall system to prepare for a future unified code version integrating IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBL DAQ test bench using a realistic front-end chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBL ROD data path implementation, test on the test bench and ROD prototypes, will be reported. Recent Pixel collaboration efforts focus on finalizing hardware and firmware tests for the IBL. The plan is to approach a complete IBL DAQ hardware-software installation by the end of 2014

Qualification of FPGA-Based Safety-Related PRM System

International Nuclear Information System (INIS)

Miyazaki, Tadashi; Oda, Naotaka; Goto, Yasushi; Hayashi, Toshifumi

2011-01-01

Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of basic logic circuits, and FPGA performs defined processing which is configured by connecting the basic logic circuit inside the FPGA. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Neutron Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development process to the other safety-related systems such as RPS from now on. Toshiba developed a special design process for NRW-FPGA-based safety-related I and C systems. The design process resolves issues for many years regarding testability of the digital system for nuclear safety application. Thus, Toshiba NRW-FPGA-based safety-related I and C systems has much advantage to be a would standard of the digital systems for nuclear safety application. (author)

Firmware development and testing of the ATLAS Pixel Detector / IBL ROD card

CERN Document Server

Gabrielli, Alessandro; The ATLAS collaboration; Balbi, Gabriele; Bindi, Marcello; Chen, Shaw-pin; Falchieri, Davide; Flick, Tobias; Hauck, Scott Alan; Hsu, Shih-Chieh; Kretz, Moritz; Kugel, Andreas; Lama, Luca; Travaglini, Riccardo; Wensing, Marius; ATLAS Pixel Collaboration

2015-01-01

The ATLAS Experiment is reworking and upgrading systems during the current LHC shut down. In particular, the Pixel detector has inserted an additional inner layer called Insertable B-Layer (IBL). The Readout-Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBLâs off-detector DAQ system. The strategy for IBL ROD firmware development was three-fold: keeping as much of the Pixel ROD datapath firmware logic as possible, employing a complete new scheme of steering and calibration firmware and designing the overall system to prepare for a future unified code version integrating IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBL DAQ testbench using realistic frontend chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBL ROD data pat...

Firmware development and testing of the ATLAS Pixel Detector / IBL ROD card

CERN Document Server

Balbi, G; The ATLAS collaboration; Gabrielli, A; Lama, L; Travaglini, R; Backhaus, M; Bindi, M; Chen, S-P; Flick, T; Kretz, M; Kugel, A; Wensing, M

2014-01-01

The ATLAS Experiment is reworking and upgrading systems during the current LHC shut down. In particular, the Pixel detector has inserted an additional inner layer called Insertable B-Layer (IBL). The Readout-Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBLâs off-detector DAQ system. The strategy for IBLROD firmware development was three-fold: keeping as much of the PixelROD datapath firmware logic as possible, employing a complete new scheme of steering and calibration firmware and designing the overall system to prepare for a future unified code version integrating IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBLDAQ testbench using realistic frontend chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBLROD data path im...

Design and development of the IBL-BOC firmware for the ATLAS Pixel IBL optical datalink system

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00356268

The Insertable $b$-Layer (IBL) is the first upgrade of the ATLAS Pixel detector at the LHC. It will be installed in the Pixel detector in 2013. The IBL will use a new sensor and readout technology, therefore the readout components of the current Pixel detector are redesigned for the readout of the IBL. In this diploma thesis the design and development of the firmware for the new IBL Back-of-Crate card (IBL-BOC) are described. The IBL-BOC is located on the off-detector side of the readout and performs the optical-electrical conversion and vice versa for the optical connection to and from the detector. To process the data transmitted to and received from the detector, the IBL-BOC uses multiple Field Programmable Gate Arrays (FPGA). The transmitted signal is a 40~Mb/s BiPhase Mark (BPM) encoded data stream, providing the timing, trigger and control to the detector. The received signal is a 160~Mb/s 8b10b encoded data stream, containing data from the detector. The IBL-BOC encodes and decodes these data streams. T...

Optimizing latency in Xilinx FPGA implementations of the GBT

Science.gov (United States)

Muschter, S.; Baron, S.; Bohm, C.; Cachemiche, J.-P.; Soos, C.

2010-12-01

The GigaBit Transceiver (GBT) [1] system has been developed to replace the Timing, Trigger and Control (TTC) system [2], currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation [3]. This code was optimized for resource utilization [4], as the GBT protocol is very demanding. It was not, however, optimized for latency â which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The latency optimization results were compared with measurement results from a Virtex 6 ML605 development board [5] equipped with a XC6VLX240T with speedgrade-1 and the package FF1156. Bit error rate tests were also performed to ensure an error free operation. The two final optimizations were analyzed for utilization and compared with the original code, distributed in the Starter Kit.

Development of FPGA-based safety-related I and C systems

Energy Technology Data Exchange (ETDEWEB)

Goto, Y.; Oda, N.; Miyazaki, T.; Hayashi, T.; Sato, T.; Igawa, S. [08, Shinsugita-cho, Isogo-ku, Yokohama 235-8523 (Japan); 1, Toshiba-cho, Fuchu, Tokyo 183-8511 (Japan)

2006-07-01

Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system [1]. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on. (authors)

Self-patching firmware program

International Nuclear Information System (INIS)

Stanchi, L.

1976-12-01

A method of branching to an auxiliary program without any hardware or software modification at the time the auxiliary program will be written is described. Suitable statements in the main program are already prepared to accept a future program that will be written in machine language. The main program is stored as firmware in PROM memory, while the auxiliary program is loaded into RAM memory. The method is described for the Intel 8080 microprocessor, but can be generalized for any microprocessor or minicomputer that uses ROMs or PROMs. 1 figure, 2 tables

Design and implementation of projects with Xilinx Zynq FPGA: a practical case

Science.gov (United States)

Travaglini, R.; D'Antone, I.; Meneghini, S.; Rignanese, L.; Zuffa, M.

The main advantage when using FPGAs with embedded processors is the availability of additional several high-performance resources in the same physical device. Moreover, the FPGA programmability allows for connect custom peripherals. Xilinx have designed a programmable device named Zynq-7000 (simply called Zynq in the following), which integrates programmable logic (identical to the other Xilinx "serie 7" devices) with a System on Chip (SOC) based on two embedded ARM processors. Since both parts are deeply connected, the designers benefit from performance of hardware SOC and flexibility of programmability as well. In this paper a design developed by the Electronic Design Department at the Bologna Division of INFN will be presented as a practical case of project based on Zynq device. It is developed by using a commercial board called ZedBoard hosting a FMC mezzanine with a 12-bit 500 MS/s ADC. The Zynq FPGA on the ZedBoard receives digital outputs from the ADC and send them to the acquisition PC, after proper formatting, through a Gigabit Ethernet link. The major focus of the paper will be about the methodology to develop a Zynq-based design with the Xilinx Vivado software, enlightening how to configure the SOC and connect it with the programmable logic. Firmware design techniques will be presented: in particular both VHDL and IP core based strategies will be discussed. Further, the procedure to develop software for the embedded processor will be presented. Finally, some debugging tools, like the embedded Logic Analyzer, will be shown. Advantages and disadvantages with respect to adopting FPGA without embedded processors will be discussed.

Software Implementation of a Secure Firmware Update Solution in an IOT Context

Directory of Open Access Journals (Sweden)

Lukas Kvarda

2016-01-01

Full Text Available The present paper is concerned with the secure delivery of firmware updates to Internet of Things (IoT devices. Additionally, it deals with the design of a safe and secure bootloader for a UHF RFID reader. A software implementation of a secure firmware update solution is performed. The results show there is space to integrate even more security features into existing devices.

Implementation of Wireless Communications Systems on FPGA-Based Platforms

Directory of Open Access Journals (Sweden)

Voros NS

2007-01-01

Full Text Available Wireless communications are a very popular application domain. The efficient implementation of their components (access points and mobile terminals/network interface cards in terms of hardware cost and design time is of great importance. This paper describes the design and implementation of the HIPERLAN/2 WLAN system on a platform including general purpose microprocessors and FPGAs. Detailed implementation results (performance, code size, and FPGA resources utilization are presented. The main goal of the design case presented is to provide insight into the design aspects of a complex system based on FPGAs. The results prove that an implementation based on microprocessors and FPGAs is adequate for the access point part of the system where the expected volumes are rather small. At the same time, such an implementation serves as a prototyping of an integrated implementation (System-on-Chip, which is necessary for the mobile terminals of a HIPERLAN/2 system. Finally, firmware upgrades were developed allowing the implementation of an outdoor wireless communication system on the same platform.

Development of FPGA-based safety-related instrumentation and control systems

Energy Technology Data Exchange (ETDEWEB)

Oda, N.; Tanaka, A.; Izumi, M.; Tarumi, T.; Sato, T. [Toshiba Corporation, Isogo Nuclear Engineering Center, Yokohama (Japan)

2004-07-01

Toshiba has developed systems which perform signal processing by field programmable gate arrays (FPGA) for safety-related instrumentation and control systems. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing units (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. Considering application to safety-related systems, nonvolatile and non rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. The systems which Toshiba developed this time are Power range Monitor (PRM) and Trip Module (TM). These systems are compatible with the conventional analog-based systems and the CPU-based systems. Therefore, requested cost for upgrading will be minimized. Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on. (authors)

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

Science.gov (United States)

Al Hassan, Mohammad; Novack, Steven D.; Hatfield, Glen S.; Britton, Paul

2017-01-01

Today's launch vehicles complex electronic and avionic systems heavily utilize the Field Programmable Gate Array (FPGA) integrated circuit (IC). FPGAs are prevalent ICs in communication protocols such as MIL-STD-1553B, and in control signal commands such as in solenoid/servo valves actuations. This paper will demonstrate guidelines to estimate FPGA failure rates for a launch vehicle, the guidelines will account for hardware, firmware, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC, FPGA memory and clock. The firmware portion will provide guidelines on the high level FPGA programming language and ways to account for software/code reliability growth. The radiation portion will provide guidelines on environment susceptibility as well as guidelines on tailoring other launch vehicle programs historical data to a specific launch vehicle.

FPGA based Smart Wireless MIMO Control System

International Nuclear Information System (INIS)

Ali, Syed M Usman; Hussain, Sajid; Siddiqui, Ali Akber; Arshad, Jawad Ali; Darakhshan, Anjum

2013-01-01

In our present work, we have successfully designed, and developed an FPGA based smart wireless MIMO (Multiple Input and Multiple Output) system capable of controlling multiple industrial process parameters such as temperature, pressure, stress and vibration etc. To achieve this task we have used Xilin x Spartan 3E FPGA (Field Programmable Gate Array) instead of conventional microcontrollers. By employing FPGA kit to PC via RF transceivers which has a working range of about 100 meters. The developed smart system is capable of performing the control task assigned to it successfully. We have also provided a provision to our proposed system that can be accessed for monitoring and control through the web and GSM as well. Our proposed system can be equally applied to all the hazardous and rugged industrial environments where a conventional system cannot work effectively

Secure firmware updates for point of sale terminals

CSIR Research Space (South Africa)

Tsague, HD

2015-03-01

Full Text Available of the equipment. In particular, there is an important cost related to the deployment of new software upgrades for the point of sale terminals, since in most cases human intervention is required. In this paper, we present a lightweight protocol for secure firmware...

Entwicklung, Implementierung and Test eines FPGA-Designs fÃ¼r die Level-1-Frontend-Elektronik des Ãusseren Spurkammersystems im LHCb-Detektor

CERN Document Server

Nedos, Mirco

For measurements of CP-violation in the B-meson system, as well as the search for new physics, the LHCb-experiment has been built at the Large Hadron Collider at CERN. One component of the sophisticated LHCb-detector is the Outer Tracker. Its measured data is transmitted serially via optical links into the readout network. For the interface between the frontend electronics on the detector and the data acquisition network a common readout board is used. This FPGA-based board, dubbed the TELL1, preprocesses the data. In this thesis the developments of the detector specific parts of the TELL1 firmware and the integration of the TELL1 board into the readout chain of the Outer Tracker are described. It covers the synchronisation and the error detection of the data received, as well as the generation of the Outer Tracker DAQ data format. In addition a zero-suppression algorithm has been implemented in the FPGA in order to reduce the network payload and guarantee operation at maximum trigger rate.

SUMAC: A monitor and control tree for multi-FPGA systems

International Nuclear Information System (INIS)

Gao, Mingshen

1999-01-01

The BTeV pixel trigger is a data acquisition system capable of finding tracks and vertices in real time in the BTeV pixel detector array. The trigger uses some 3000 processing elements (DSPs) arranged in three processing levels to handle a raw data rate of nearly 100 Gigabytes per second and bring the trigger rate down to 10 KHz. The trigger system has more than 6000 programmable elements, including Field Programmable Logic Arrays (FPGAs), microprocessors (DSPs, interface to the monitor and control tree through FPGAs), and others. Sumac (Serial Utility Monitor and Control tree) is used for configuring and monitoring of these devices. Its primary function is the downloading of FPGA bit streams, microprocessor programs, chip configurations, and test data. In addition, remote cpus and other devices can send messages and status back to the host. The Sumac system is capable of handling several thousand remote devices from a single host PC. Because it stores configuration data in local flash eeproms, it will be capable of achieving a complete system reboot in less than 1 second. The Sumac system is a tree hierarchy connected via high-speed serial links. Typically each board in the system will have a control node which accepts a single upstream serial link and fans out to as many as 32 downstream links. The downstream links can connect to FPGAs or to other control nodes for further fanout

Logic qualification of FPGA-based safety-related I and C systems

International Nuclear Information System (INIS)

Hayashi, Toshifumi; Oda, Naotaka; Ito, Toshiaki; Miyazaki, Tadashi; Haren, Yasuhiko

2009-01-01

We established a logic qualification method for FPGA-Based I and C safety-related use in Nuclear Power Plants Systems. The FPGA is a programmable logic device and has advantages that the programming is rigorous, simple verifiable, and the technology is stable. However, logic qualification of FPGA had been an issue to be solved when it is used in the safety-related systems, because FPGA is relatively new technology for the nuclear power industry. We employed a software-life cycle approach, because its development process is similar to that of conventional computer-based systems. There are some differences between the FPGA-Based systems and the computer-based systems in the implementation and integration of logic. We examined the FPGA logic implementation and integration process to identify any FPGA-Based system specific hazards. The identified hazards are (1) small logic errors, (2) timing errors, (3) logic synthesis errors, (4) place and route errors, and (5) logic embedding errors. We took the appropriate countermeasures to mitigate these hazards, and employed this logic qualification method in the qualification of the Power Range Monitor System for BWR Power Plants. (author)

Synthesis of blind source separation algorithms on reconfigurable FPGA platforms

Science.gov (United States)

Du, Hongtao; Qi, Hairong; Szu, Harold H.

2005-03-01

-Specific Integrated Circuit (ASIC) using standard-height cells. ICA is an algorithm that can solve BSS problems by carrying out the all-order statistical, decorrelation-based transforms, in which an assumption that neighborhood pixels share the same but unknown mixing matrix A is made. In this paper, we continue our investigation on the design challenges of firmware approaches to smart algorithms. We think two levels of parallelization can be explored, including pixel-based parallelization and the parallelization of the restoration algorithm performed at each pixel. This paper focuses on the latter and we use ICA as an example to explain the design and implementation methods. It is well known that the capacity constraints of single FPGA have limited the implementation of many complex algorithms including ICA. Using the reconfigurability of FPGA, we show, in this paper, how to manipulate the FPGA-based system to provide extra computing power for the parallelized ICA algorithm with limited FPGA resources. The synthesis aiming at the pilchard re-configurable FPGA platform is reported. The pilchard board is embedded with single Xilinx VIRTEX 1000E FPGA and transfers data directly to CPU on the 64-bit memory bus at the maximum frequency of 133MHz. Both the feasibility performance evaluations and experimental results validate the effectiveness and practicality of this synthesis, which can be extended to the spatial-variant jitter restoration for micro-UAV deployment.

The Impact of Hard Disk Firmware Steganography on Computer Forensics

Directory of Open Access Journals (Sweden)

Iain Sutherland

2009-06-01

Full Text Available The hard disk drive is probably the predominant form of storage media and is a primary data source in a forensic investigation. The majority of available software tools and literature relating to the investigation of the structure and content contained within a hard disk drive concerns the extraction and analysis of evidence from the various file systems which can reside in the user accessible area of the disk. It is known that there are other areas of the hard disk drive which could be used to conceal information, such as the Host Protected Area and the Device Configuration Overlay. There are recommended methods for the detection and forensic analysis of these areas using appropriate tools and techniques. However, there are additional areas of a disk that have currently been overlooked.ÃÂ The Service Area or Platter Resident Firmware Area is used to store code and control structures responsible for the functionality of the drive and for logging failing or failed sectors.This paper provides an introduction into initial research into the investigation and identification of issues relating to the analysis of the Platter Resident Firmware Area. In particular, the possibility that the Platter Resident Firmware Area could be manipulated and exploited to facilitate a form of steganography, enabling information to be concealed by a user and potentially from a digital forensic investigator.

Real-time beam monitoring in scanned proton therapy

Science.gov (United States)

Klimpki, G.; Eichin, M.; Bula, C.; Rechsteiner, U.; Psoroulas, S.; Weber, D. C.; Lomax, A.; Meer, D.

2018-05-01

When treating cancerous tissues with protons beams, many centers make use of a step-and-shoot irradiation technique, in which the beam is steered to discrete grid points in the tumor volume. For safety reasons, the irradiation is supervised by an independent monitoring system validating cyclically that the correct amount of protons has been delivered to the correct position in the patient. Whenever unacceptable inaccuracies are detected, the irradiation can be interrupted to reinforce a high degree of radiation protection. At the Paul Scherrer Institute, we plan to irradiate tumors continuously. By giving up the idea of discrete grid points, we aim to be faster and more flexible in the irradiation. But the increase in speed and dynamics necessitates a highly responsive monitoring system to guarantee the same level of patient safety as for conventional step-and-shoot irradiations. Hence, we developed and implemented real-time monitoring of the proton beam current and position. As such, we read out diagnostic devices with 100 kHz and compare their signals against safety tolerances in an FPGA. In this paper, we report on necessary software and firmware enhancements of our control system and test their functionality based on three exemplary error scenarios. We demonstrate successful implementation of real-time beam monitoring and, consequently, compliance with international patient safety regulations.

A new FPGA-based time-over-threshold system for the time of flight detectors at the BGO-OD experiment

Energy Technology Data Exchange (ETDEWEB)

Freyermuth, Oliver [Physikalisches Institut, Nussallee 12, D-53115 Bonn (Germany); Collaboration: BGO-OD-Collaboration

2015-07-01

The BGO-OD experiment at the ELSA accelerator facility at Bonn is built for the systematic investigation of meson photoproduction in the GeV region. It features the unique combination of a central, highly segmented BGO crystal calorimeter covering almost 4Ï in acceptance and a forward magnetic spectrometer complemented by time of flight walls. The readout of the ToF scintillator bars was upgraded to an FPGA-based VME-board equipped with discriminator mezzanines including per-channel remotely adjustable thresholds. A firmware was developed combining a time-over-threshold (ToT) measurement by implementing a dual-edge TDC, a configurable meantimer trigger logic including a special cosmics trigger, adjustable input delays and gateable scalers, all inside a single electronics module. An experimentally obtained relation between ToT and slope of a PMT signal can be used for a time walk correction to achieve time resolutions comparable to a classical chain of CFD and standard TDC. Additionally, the time-over-threshold information can be exploited for gain matching and allows to monitor online the gain-stability and check for electronics problems such as pulse reflections or baseline jitter. The system is well-suited for a wide range of PMT-based fast detectors with many channels and further applications foreseen.

The CMS Beam Halo Monitor electronics

International Nuclear Information System (INIS)

Tosi, N.; Fabbri, F.; Montanari, A.; Torromeo, G.; Dabrowski, A.E.; Orfanelli, S.; Grassi, T.; Hughes, E.; Mans, J.; Rusack, R.; Stifter, K.; Stickland, D.P.

2016-01-01

The CMS Beam Halo Monitor has been successfully installed in the CMS cavern in LHC Long Shutdown 1 for measuring the machine induced background for LHC Run II. The system is based on 40 detector units composed of synthetic quartz Cherenkov radiators coupled to fast photomultiplier tubes (PMTs). The readout electronics chain uses many components developed for the Phase 1 upgrade to the CMS Hadronic Calorimeter electronics, with dedicated firmware and readout adapted to the beam monitoring requirements. The PMT signal is digitized by a charge integrating ASIC (QIE10), providing both the signal rise time, with few nanosecond resolution, and the charge integrated over one bunch crossing. The backend electronics uses microTCA technology and receives data via a high-speed 5 Gbps asynchronous link. It records histograms with sub-bunch crossing timing resolution and is read out via IPbus using the newly designed CMS data acquisition for non-event based data. The data is processed in real time and published to CMS and the LHC, providing online feedback on the beam quality. A dedicated calibration monitoring system has been designed to generate short triggered pulses of light to monitor the efficiency of the system. The electronics has been in operation since the first LHC beams of Run II and has served as the first demonstration of the new QIE10, Microsemi Igloo2 FPGA and high-speed 5 Gbps link with LHC data

FPGA design

CERN Document Server

Simpson, Philip

2010-01-01

This book describes best practices for successful FPGA design. It is the result of the author's meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book's content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design t

Commercial FPGA based multipurpose controller: implementation perspective

International Nuclear Information System (INIS)

Arredondo, I.; Campo, M. del; Echevarria, P.; Belver, D.; Muguira, L.; Garmendia, N.; Hassanzadegan, H.; Eguiraun, M.; Jugo, J.; Etxebarria, V.

2012-01-01

This work presents a fast acquisition multipurpose controller, focussing on its EPICS integration and on its XML based configuration. This controller is based on a Lyrtech VHS-ADC board which encloses an FPGA, connected to a Host PC. This Host acts as local controller and implements an IOC integrating the device in an EPICS network. These tasks have been performed using Java as the main tool to program the PC to make the device fit the desired application. All the process includes the use of different technologies: JNA to handle C functions i.e. FPGA API, JavaIOC to integrate EPICS and XML w3c DOM classes to easily configure the particular application. In order to manage the functions, Java specific tools have been developed: Methods to manage the FPGA (read/write registers, acquire data,...), methods to create and use the EPICS server (put, get, monitor,...), mathematical methods to process the data (numeric format conversions,...) and methods to create/ initialize the application structure by means of an XML file (parse elements, build the DOM and the specific application structure). This XML file has some common nodes and tags for all the applications: FPGA registers specifications definition and EPICS variables. This means that the user only has to include a node for the specific application and use the mentioned tools. A main class is in charge of managing the FPGA and EPICS server according to this XML file. This multipurpose controller has been successfully used to implement a BPM and an LLRF application for the ESS-Bilbao (European Spallation Source) facility. (authors)

Factors Influencing the Decision to Proceed to Firmware Upgrades to Implanted Pacemakers for Cybersecurity Risk Mitigation.

Science.gov (United States)

Saxon, Leslie A; Varma, Niraj; Epstein, Laurence M; Ganz, Leonard I; Epstein, Andrew E

2018-05-10

In August 2017, the first major recall for cybersecurity vulnerabilities in pacemakers capable of remote connectivity was released that impacted 465,000 United States patients. 1,2 The FDA approved a firmware update designed by the manufacturer of the devices as a remediation (Abbott , formally St. Jude Medical). The recall was in response to the public disclosure of vulnerability by an investment firm and produced in a lab environment that could allow an unauthorized party in close proximity to a patient to impact the performance of the device or modify device settings via radio frequency communication. 3 While an exploit has not occurred in a patient and requires a high degree of resources and skill to execute, if accomplished, it could pose a significant risk to device safety and essential performance and cause patient harm. The FDA defines this as an uncontrolled vulnerability. 2 The recall recommendations were coordinated between the FDA, the Industrial Control Systems Cyber Emergency Response Team (ICS-CERT), a division of Homeland Security that responds to and coordinates disclosure of critical infrastructure cybersecurity vulnerabilities and Abbott. 1 All parties urged caution and shared decision making between patient and clinician as to whether to have the device firmware update, a process that requires a clinic visit to implement with a device programmer. The manufacturer bench tested the firmware update but the only prior experience with an implanted device firmware updates was a 2012 ICD firmware update that demonstrated a 0.197% risk of device back-up mode pacing after the upgrade was performed.

Verification of FPGA-Signal using the test board which is applied to Safety-related controller

Energy Technology Data Exchange (ETDEWEB)

Chung, Youn-Hu; Yoo, Kwanwoo; Lee, Myeongkyun; Yun, Donghwa [SOOSAN ENS, Seoul (Korea, Republic of)

2016-10-15

This article aims to provide the verification method for BGA-type FPGA of Programmable Logic Controller (PLC) developed as Safety Class. The logic of FPGA in the control device with Safety Class is the circuit to control overall logic of PLC. Saftety-related PLC must meet the international standard specifications. With this reason, we use V and V according to an international standard in order to secure high reliability and safety. By using this, we are supposed to proceed to a variety of verification courses for extra reliability and safety analysis. In order to have efficient verification of test results, we propose the test using the newly changed BGA socket which can resolve the problems of the conventional socket on this paper. The Verification of processes is divided into verification of Hardware and firmware. That processes are carried out in the unit testing and integration testing. The proposed test method is simple, the effect of cost reductions by batch process. In addition, it is advantageous to measure the signal from the Hi-speed-IC due to its short length of the pins and it was plated with the copper around it. Further, it also to prevent abrasion on the IC ball because it has no direct contact with the PCB. Therefore, it can be actually applied is to the BGA package test and we can easily verify logic as well as easily checking the operation of the designed data.

EXPERIENCE WITH FPGA-BASED PROCESSOR CORE AS FRONT-END COMPUTER

International Nuclear Information System (INIS)

HOFF, L.T.

2005-01-01

The RHIC control system architecture follows the familiar ''standard model''. LINUX workstations are used as operator consoles. Front-end computers are distributed around the accelerator, close to equipment being controlled or monitored. These computers are generally based on VMEbus CPU modules running the VxWorks operating system. I/O is typically performed via the VMEbus, or via PMC daughter cards (via an internal PCI bus), or via on-board I/O interfaces (Ethernet or serial). Advances in FPGA size and sophistication now permit running virtual processor ''cores'' within the FPGA logic, including ''cores'' with advanced features such as memory management. Such systems offer certain advantages over traditional VMEbus Front-end computers. Advantages include tighter coupling with FPGA logic, and therefore higher I/O bandwidth, and flexibility in packaging, possibly resulting in a lower noise environment and/or lower cost. This paper presents the experience acquired while porting the RHIC control system to a PowerPC 405 core within a Xilinx FPGA for use in low-level RF control

Field Programmable Gate Array (FPGA Respiratory Monitoring System Using a Flow Microsensor and an Accelerometer

Directory of Open Access Journals (Sweden)

Mellal Idir

2017-04-01

Full Text Available This paper describes a non-invasive system for respiratory monitoring using a Micro Electro Mechanical Systems (MEMS flow sensor and an IMU (Inertial Measurement Unit accelerometer. The designed system is intended to be wearable and used in a hospital or at home to assist people with respiratory disorders. To ensure the accuracy of our system, we proposed a calibration method based on ANN (Artificial Neural Network to compensate the temperature drift of the silicon flow sensor. The sigmoid activation functions used in the ANN model were computed with the CORDIC (COordinate Rotation DIgital Computer algorithm. This algorithm was also used to estimate the tilt angle in body position. The design was implemented on reconfigurable platform FPGA.

FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

Directory of Open Access Journals (Sweden)

Millar James

2006-01-01

Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

Directory of Open Access Journals (Sweden)

James Millar

2006-10-01

Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

The FPGA Pixel Array Detector

International Nuclear Information System (INIS)

Hromalik, Marianne S.; Green, Katherine S.; Philipp, Hugh T.; Tate, Mark W.; Gruner, Sol M.

2013-01-01

A proposed design for a reconfigurable x-ray Pixel Array Detector (PAD) is described. It operates by integrating a high-end commercial field programmable gate array (FPGA) into a 3-layer device along with a high-resistivity diode detection layer and a custom, application-specific integrated circuit (ASIC) layer. The ASIC layer contains an energy-discriminating photon-counting front end with photon hits streamed directly to the FPGA via a massively parallel, high-speed data connection. FPGA resources can be allocated to perform user defined tasks on the pixel data streams, including the implementation of a direct time autocorrelation function (ACF) with time resolution down to 100 ns. Using the FPGA at the front end to calculate the ACF reduces the required data transfer rate by several orders of magnitude when compared to a fast framing detector. The FPGA-ASIC high-speed interface, as well as the in-FPGA implementation of a real-time ACF for x-ray photon correlation spectroscopy experiments has been designed and simulated. A 16Ã16 pixel prototype of the ASIC has been fabricated and is being tested. -- Highlights: âº We describe the novelty and need for the FPGA Pixel Array Detector. âº We describe the specifications and design of the Diode, ASIC and FPGA layers. âº We highlight the Autocorrelation Function (ACF) for speckle as an example application. âº Simulated FPGA output calculates the ACF for different input bitstreams to 100 ns. âº Reduced data transfer rate by 640Ã and sped up real-time ACF by 100Ã other methods.

SEU mitigation exploratory tests in a ITER related FPGA

International Nuclear Information System (INIS)

Batista, Antonio J.N.; Leong, Carlos; Santos, Bruno; Fernandes, Ana; Ramos, Ana Rita; Santos, Joana P.; Marques, JosÃ© G.; Teixeira, Isabel C.; Teixeira, JoÃ£o P.; Sousa, Jorge; GonÃ§alves, Bruno

2017-01-01

Data acquisition hardware of ITER diagnostics if located in the port cells of the tokamak, as an example, will be irradiated with neutrons during the fusion reactor operation. Due to this reason the majority of the hardware containing Field Programmable Gate Arrays (FPGA) will be placed after the ITER bio-shield, such as the cubicles instrumentation room. Nevertheless, it is worth to explore real-time mitigation of soft-er