||| An Idealised HDL for linear wirings.
|||
||| Module    : Idealised.idr
||| Copyright : (c) Jan de Muijnck-Hughes
||| License   : see LICENSE
|||
module Circuits.Idealised

import public Circuits.Idealised.Core
import public Circuits.Idealised.Types
import public Circuits.Idealised.Terms
import public Circuits.Idealised.AST
import public Circuits.Idealised.Lexer
import public Circuits.Idealised.Parser
import public Circuits.Idealised.Check
import public Circuits.Idealised.Interp

-- [ EOF ]
