John R. Hauser
2019 July 29
1. Introduction 2. Limitations 3. Acknowledgments and License 4. HardFloat Package Directory Structure 5. Specializing the HardFloat Modules to Test 6. Dependence on Berkeley TestFloat 7. Makefile
Test Targets7.1. Testing Conversions Between Standard and Recoded Floating-Point ( fNToRecFN
andrecFNToFN
)7.2. Testing Conversions from Integer ( iNToRecFN
)7.3. Testing Conversions to Integer ( recFNToIN
)7.4. Testing Conversions Between Formats ( recFNToRecFN
)7.5. Testing Addition and Subtraction ( addRecFN
)7.6. Testing Multiplication ( mulRecFN
)7.7. Testing Fused Multiply-Add ( mulAddRecFN
)7.8. Testing Division and Square Root ( divSqrtRecFN_small
)7.9. Testing Comparisons ( compareRecFN
)7.10. Testing Multiple Functions 8. Interpreting the Test Output 9. Contact Information
This document provides instructions for testing Berkeley HardFloat using
Verilator and the test infrastructure supplied in the HardFloat package.
Berkeley HardFloat is a hardware implementation of binary floating-point
conforming to the IEEE Standard for Floating-Point Arithmetic.
For basic documentation about HardFloat, see
HardFloat-Verilog.html
Verilator is a free tool for converting a subset of synthesizable Verilog or
SystemVerilog into C++ code.
It is also possible to test HardFloat using a Verilog simulator, as documented
in
HardFloat-test-Verilog.html
The supplied tests for HardFloat depend on Berkeley TestFloat, which is not included in the HardFloat package. TestFloat in turn depends on Berkeley SoftFloat. The TestFloat and SoftFloat packages can be obtained from these Web pages:
http://www.jhauser.us/arithmetic/TestFloat.html
http://www.jhauser.us/arithmetic/SoftFloat.html
The supplied testbench can test only the common IEEE-defined formats supported
by TestFloat, which are
The Makefile
provided for running tests requires GNU
make
or a very close relative.
Adapting the testbench to overcome either of these limitations is possible but far from trivial.
The HardFloat package was written by me,
Par Lab: Microsoft (Award #024263), Intel (Award #024894), and U.C. Discovery (Award #DIG07-10227), with additional support from Par Lab affiliates Nokia, NVIDIA, Oracle, and Samsung. ASPIRE Lab: DARPA PERFECT program (Award #HR0011-12-2-0016), with additional support from ASPIRE industrial sponsor Intel and ASPIRE affiliates Google, Nokia, NVIDIA, Oracle, and Samsung. ADEPT Lab: ADEPT industrial sponsor Intel and ADEPT affiliates Google, Futurewei, Seagate, Siemens, and SK Hynix.
The following applies to the whole of HardFloat
Copyright 2019 The Regents of the University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution.
Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

The directory structure for the Verilog version of HardFloat is as follows:
doc source 8086-SSE ARM-VFPv2 RISCV test source Verilator build Verilator-GCC IcarusVerilog
The source files that define HardFloat’s modules are in the main
source
directory.
The test
directory has additional files used solely for testing.
The test sources are of course all in test/source
, while the
test/build
subdirectory contains a couple of example build
targets.
For testing using Verilator, the relevant build target subdirectory is
Verilator-GCC
IcarusVerilog
, provides an example of
using a Verilog simulator instead of Verilator.)
As the name Verilator-GCC
test/source/Verilator
.
It is possible to use a different C++ compiler by copying and modifying the
Verilator-GCC
As supplied, subdirectory Verilator-GCC
Makefile config.make config.h
used to build and execute all tests.
The Makefile
is written solely for GNU make
.
Another make
variant is unlikely to work unless it is highly
GNU-compatible.
To determine the particular HardFloat variant to test, the testbench requires
that a Makefile
macro, SPECIALIZE_TYPE
, be defined
with the name of a selected specialization subdirectory within
HardFloat’s main source
directory.
As explained in
HardFloat-Verilog.html
8086-SSE ARM-VFPv2 RISCV
Macro SPECIALIZE_TYPE
can be defined either by editing the file
config.make
found in the Verilator-GCC
Makefile
, or by providing a definition for
SPECIALIZE_TYPE
among the arguments to the make
command.
The HardFloat testbench depends on Berkeley TestFloat, which must be obtained
and built separately.
The latest version of TestFloat is available at Web page
http://www.jhauser.us/arithmetic/TestFloat.html
The testbench expects the reference floating-point used by TestFloat to
exactly match the options chosen for building HardFloat.
TestFloat’s reference floating-point is provided by the Berkeley
SoftFloat library, which again must be obtained and built separately.
The Web page for SoftFloat is
http://www.jhauser.us/arithmetic/SoftFloat.html
The testbench Makefile
requires that program
testfloat_gen
be directly executable by the make
program.
Usually this is achieved by modifying your PATH
environment
variable to include the directory containing testfloat_gen
.
Makefile
Test Targets
The Makefile
in test/build/
is the driver for building and executing tests.
This Makefile
supports a number of possible targets, each testing
one or more HardFloat functions for all relevant rounding modes and other
control parameters.
In all cases, tests ultimately involve executing one or more commands of the
form
testfloat_gen ... <function> | <module-test-program> <control-args>
The vertical bar (|
) represents a pipe from the
testfloat_gen
program, which provides a sequence of test operands
and expected results, to a second program that both simulates the specific
module being tested and confirms that its output matches what
testfloat_gen
expected.
The code for simulating a HardFloat module is of course provided by Verilator,
translating from the original Verilog.
The <control-args>
control
and roundingMode
,
depending on the module being tested.
Many Makefile
targets are supported for running various sets of
tests.
The basic ones for testing individual HardFloat modules are these:
test-<level>-fNToRecFN test-<level>-recFNToFN test-<level>-iNToRecFN test-<level>-recFNToIN test-<level>-recFNToRecFN test-<level>-addRecFN_add test-<level>-addRecFN_sub test-<level>-addRecFN test-<level>-mulRecFN test-<level>-mulAddRecFN_add test-<level>-mulAddRecFN_mul test-<level>-mulAddRecFN test-<level>-divSqrtRecFN_small_div test-<level>-divSqrtRecFN_small_sqrt test-<level>-compareRecFN
where <level>
is always either
‘level1
’ or ‘level2
’.
The <level>
component directly controls the
-level
option given to testfloat_gen
, which
determines the number and depth of tests performed.
For example, the command to execute the complete set of
“addRecFN
is
make test-level2-addRecFN
Each test is performed for all formats supported by TestFloat (and for only
those formats), which for floating-point is IEEE
The Makefile
targets listed above are further dissected in
subsections below.
Other targets are supported that automatically test more than one module in sequence:
test-<level>-all1 test-<level>-all2 test-<level>
For more about these, see subsection 7.10 below, Testing Multiple Functions.
The supplied tests all report status and error information in a common way. As it executes, each test writes status information to the standard error output, which should be the terminal screen by default. In order for this status to be displayed properly, the standard error stream should not be redirected to a file. Any discrepancies that are found are written to the standard output stream, which is easily redirected to a file if desired. Unless redirected, reported errors will appear intermixed with the ongoing status information in the output.
fNToRecFN
and recFNToFN
)
HardFloat modules fNToRecFN
and recFNToFN
are tested
by Makefile
targets
test-<level>-fNToRecFN test-<level>-recFNToFN
Testing can be restricted to a single TestFloat-supported format with one of
these Makefile
targets:
test-<level>-f16ToRecF16 test-<level>-f32ToRecF32 test-<level>-f64ToRecF64 test-<level>-f128ToRecF128 test-<level>-recF16ToF16 test-<level>-recF32ToF32 test-<level>-recF64ToF64 test-<level>-recF128ToF128
iNToRecFN
)
Module iNToRecFN
is tested by Makefile
targets
test-<level>-iNToRecFN
Conversions from all source integer formats supported by TestFloat are tested, encompassing integers of sizes 32 bits and 64 bits, both unsigned and signed.
Testing can be restricted to a single integer size and a single floating-point
destination format with one of these Makefile
targets:
test-<level>-i32ToRecF16 test-<level>-i32ToRecF32 test-<level>-i32ToRecF64 test-<level>-i32ToRecF128 test-<level>-i64ToRecF16 test-<level>-i64ToRecF32 test-<level>-i64ToRecF64 test-<level>-i64ToRecF128
Each target tests conversions from both unsigned and signed integers of the specified size.
recFNToIN
)
Module recFNToIN
is tested by Makefile
targets
test-<level>-recFNToIN
Conversions to all destination integer formats supported by TestFloat are tested, encompassing integers of sizes 32 bits and 64 bits, both unsigned and signed.
Testing can be restricted to a single floating-point source format and a single
integer destination size with one of these Makefile
targets:
test-<level>-recF16ToI32 test-<level>-recF16ToI64 test-<level>-recF32ToI32 test-<level>-recF32ToI64 test-<level>-recF64ToI32 test-<level>-recF64ToI64 test-<level>-recF128ToI32 test-<level>-recF128ToI64
Each target tests conversions to both unsigned and signed integers of the specified size.
recFNToRecFN
)
Makefile
targets
test-<level>-recFNToRecFN
test module recFNToRecFN
.
Testing can be restricted to a single source format and single destination format using one of these targets:
test-<level>-recF16ToRecF32 test-<level>-recF16ToRecF64 test-<level>-recF16ToRecF128 test-<level>-recF32ToRecF16 test-<level>-recF32ToRecF64 test-<level>-recF32ToRecF128 test-<level>-recF64ToRecF16 test-<level>-recF64ToRecF32 test-<level>-recF64ToRecF128 test-<level>-recF128ToRecF16 test-<level>-recF128ToRecF32 test-<level>-recF128ToRecF64
addRecFN
)
Makefile
targets
test-<level>-addRecFN_add test-<level>-addRecFN_sub
test module addRecFN
, for input
subOp
= 0subOp
= 1
test-<level>-addRecFN
combine both sets of tests (both addition and subtraction).
Testing can be restricted to a single TestFloat-supported format with one of
these Makefile
targets:
test-<level>-addRecF16_add test-<level>-addRecF32_add test-<level>-addRecF64_add test-<level>-addRecF128_add test-<level>-addRecF16_sub test-<level>-addRecF32_sub test-<level>-addRecF64_sub test-<level>-addRecF128_sub test-<level>-addRecF16 test-<level>-addRecF32 test-<level>-addRecF64 test-<level>-addRecF128
mulRecFN
)
Module mulRecFN
is tested by Makefile
targets
test-<level>-mulRecFN
Testing can be restricted to a single TestFloat-supported format with one of these targets:
test-<level>-mulRecF16 test-<level>-mulRecF32 test-<level>-mulRecF64 test-<level>-mulRecF128
mulAddRecFN
)
Module mulAddRecFN
is tested by Makefile
targets
test-<level>-mulAddRecFN
However, testing is currently done only for input
op
= 0testfloat_gen
can supply test inputs.
Additional special targets,
test-<level>-mulAddRecFN_add test-<level>-mulAddRecFN_mul
exist for testing mulAddRecFN
in the roles of just addition
(a
× 1 + c
a
× b
+ 0mulAddRecFN
is expected to behave the same
as addRecFN
and mulRecFN
respectively (except
possibly for specific NaN payload propagation in the case of addition).
Testing can be restricted to a single TestFloat-supported format with one of these targets:
test-<level>-mulAddRecF16 test-<level>-mulAddRecF32 test-<level>-mulAddRecF64 test-<level>-mulAddRecF128 test-<level>-mulAddRecF16_add test-<level>-mulAddRecF32_add test-<level>-mulAddRecF64_add test-<level>-mulAddRecF128_add test-<level>-mulAddRecF16_mul test-<level>-mulAddRecF32_mul test-<level>-mulAddRecF64_mul test-<level>-mulAddRecF128_mul
divSqrtRecFN_small
)
Makefile
targets
test-<level>-divSqrtRecFN_small_div test-<level>-divSqrtRecFN_small_sqrt
test module divSqrtRecFN_small
, for input
sqrtOp
= 0sqrtOp
= 1
Testing can be restricted to a single TestFloat-supported format with one of these targets:
test-<level>-divSqrtRecF16_small_div test-<level>-divSqrtRecF32_small_div test-<level>-divSqrtRecF64_small_div test-<level>-divSqrtRecF128_small_div test-<level>-divSqrtRecF16_small_sqrt test-<level>-divSqrtRecF32_small_sqrt test-<level>-divSqrtRecF64_small_sqrt test-<level>-divSqrtRecF128_small_sqrt
compareRecFN
)
Module compareRecFN
is tested by Makefile
targets
test-<level>-compareRecFN
These targets test the module’s outputs against TestFloat’s
comparison functions, lt
, le
, and eq
.
Like all the others, testing can be restricted to a single format with one of these targets:
test-<level>-compareRecF16 test-<level>-compareRecF32 test-<level>-compareRecF64 test-<level>-compareRecF128
A few Makefile
targets combine larger collections of HardFloat
functions.
Targets named
test-<level>-all1
test all of the “one-operand” functions, the same as covered by these targets:
test-<level>-fNToRecFN test-<level>-recFNToFN test-<level>-iNToRecFN test-<level>-recFNToIN test-<level>-recFNToRecFN test-<level>-divSqrtRecFN_small_sqrt
Likewise, the “two-operand” functions can all be tested using
Makefile
targets
test-<level>-all2
which combine these targets:
test-<level>-addRecFN test-<level>-mulRecFN test-<level>-mulAddRecFN_add test-<level>-mulAddRecFN_mul test-<level>-divSqrtRecFN_small_div test-<level>-compareRecFN
Lastly, the simplest of Makefile
targets,
test-<level>
encompass all defined tests at a given level, being a combination of:
test-<level>-all1 test-<level>-all2 test-<level>-mulAddRecFN
The “errors” reported by the HardFloat tests may or may not really represent errors in HardFloat. For each test case tried, the results from HardFloat could differ from the expected results for several reasons:
It is the responsibility of the user to determine the causes for the discrepancies that are reported. Making this determination can require detailed knowledge about both the IEEE Standard and HardFloat’s recoded floating-point format. Assuming both TestFloat and the Verilator testbench are working properly, any differences found will be due to either the first or last of the reasons above.
For each reported error (or apparent error), a line of text is written to the default output. If a line would be longer than 79 characters, it is divided. The first part of each error line begins in the leftmost column, and any subsequent “continuation” lines are indented with a tab.
Each error reported is of the form:
<inputs> => <observed-output> expected <expected-output>
The <inputs>
are the inputs to the operation.
Each output (observed or expected) is shown as a pair: the result value first,
followed by the exception flags.
For example, two typical error lines could be
140FFFE00 180000100 => 041000000 03 expected 041000000 01 081000004 03FFFFFF8 => 041000000 03 expected 041000000 01
In the first line, the inputs are 140FFFE00
and
180000100
, and the observed result is 041000000
with
flags 03
.
TestFloat’s result is the same but with different flags, 01
.
The two instances above were reported as errors because the exception flag
results differ.
Each input and output value, including exception flags, is represented in raw
hexadecimal.
Floating-point inputs and outputs to HardFloat modules are usually encoded in
HardFloat’s recoded form, so they appear in this form, not in a standard
IEEE format.
The only exceptions to this rule are the fNToRecFN
tests, for
which the input is in a standard IEEE format, and the recFNToFN
tests, for which the output is in a standard format.
At the time of this writing, the most up-to-date information about HardFloat
and the latest release can be found at the Web page
http://www.jhauser.us/arithmetic/HardFloat.html


Lil Baby Hopes To "Catch The Sun" On "Queen & Slim Soundtrack" Single
by Erika MarieCatch The Sun
Lil Baby
Editor Rating: HOTTTTT
User Rating: meh - 58% (6)
Lauryn Hill's Queen & Slim Soundtrack single "Guarding the Gates" was but only one gem from the feature film's musical collection. Lil Baby has also added his vocals to the soundtrack on a single titled "Catch the Sun." The Atlanta rapper's solo single was produced by recognized artist Hit-Boy and is a glimpse into the film's unfolding storyline.
Queen & Slim is set to hit theaters on November 27 and follows the tale of a couple, Daniel Kaluuya and Jodie Turner-Smith, who are stuck on an uneventful first date. Kaluuya's character ends up shooting and killing a bigoted, violent police officer, so the couple decides to go on the run. The encounter with the cop is played in the media, and the pair is dubbed to be cop-killing fugitives. However, the story follows their encounters with random people who help, and teach, them throughout their journey of freedom and love.
Quotable Lyrics
If it ain't color, what's the difference between you and I?


Documents
Real-time
Java in Avionics Applications [pdf]
Proceedings of the 12th IEEE Real-Time and Embedded
Technology and Applications Symposium (RTAS), 2006.
Engineering
a Customizable Intermediate Representation [pdf]
Science of Computer Programming, to appear 2005,
(supercedes "Engineering
a Customizable
Intermediate
Representation" in
theWorkshop
on Interpreters,
Virtual Machines
and Emulators,
(IVME'03).)
Preemptible
Atomic Regions for Real-time Java [pdf]
Proceedings of the 26th IEEE International Real-Time
Systems Symposium (RTSS05), 2005.
PolyD: A Flexible Dispatching Framework> [pdf]
Proceedings of the ACM SIGPLAN Conference on Object-Oriented
Programming Systems, Languages and Applications (OOPSLA'05), 2005.
Engineering a Customizable Intermediate Representation
Presented at IVME 2003
This paper presents the design of the Ovm intermediate representation
and how various Ovm components are build based upon the IR specification.
Idioms in Ovm
Technical Report No. CSD-TR-03-017, Department
of Computer Sciences, Purdue University (ps)
This paper presents the idioms used in Ovm to efficiently
express non-Java behaviors and compares the Ovm approach with design
characteristics of JikesRVM.
Scoped Types for Real-time Java [pdf]
Proceedings of the 25th IEEE International Real-Time
Systems Symposium (RTSS04), 2004.
Real-Time Java Scoped Memory: Design Patterns
and Semantics [pdf]
Proceedings of the 7th IEEE International Symposium
on Object-oriented Real-time distributed Computing, (ISORC 2004),
2004.
Subtype tests in real time [pdf]
Proceedings of the European Conference on Object
Oriented Programming (ECOOP'03), 2003.
Walkabout Revisted: The Runabout
Presented at ECOOP 2003
This paper presents a variation of the visitor patter which allows
programmers to write visitor-like code in a concise way. The Runabout
is a library extension which adds a limited form of multi-dispatch
without requiring changes to Java syntax or the compiler
Incommunicado: Fast Communication for Isolates [pdf]
Proceedings of the ACM SIGPLAN Conference on Object
Oriented Programming, Systems, Languages and Applications (OOPSLA'02).
Encapsulating Objects with Confined Types [pdf]
Proceedings of the 2001 ACM SIGPLAN Conference
on Object Oriented Programming, Systems, Languages and Applications
(OOPSLA'01)


public class GameMain
extends javafx.application.Application
| Modifier and Type | Field and Description |
|---|---|
private java.lang.String |
arialFont |
private static javafx.scene.shape.Path |
arrow |
private javafx.scene.paint.Paint |
arrowColor |
private int |
arrowHeadSize |
private int |
arrowWidth |
private javafx.scene.paint.Paint |
attackHighlightColor |
private java.util.ArrayList<Attack> |
attackList |
private java.lang.String |
buttonBackgroundColor |
private int |
buttonHeight |
private int |
buttonSpacing |
private javafx.scene.paint.Paint |
buttonTextColor |
private int |
buttonWidth |
private int |
buttonYPadding |
private static javafx.scene.control.Label |
description |
private static javafx.scene.control.Label |
descriptionHead |
private java.lang.String |
descriptionHeadFontSize |
private int |
descriptionHeadHeigth |
private int |
descriptionXPadding |
private int |
descriptionYPadding |
private com.jfoenix.controls.JFXButton |
endTurnButton |
private java.lang.String |
fontSize32 |
private GameLogic |
game |
private boolean |
gameFinished |
private int |
gameOverContentSpacing |
private int |
gameOverHeight |
private int |
gameOverWidth |
private int |
gridXPadding |
private int |
gridYPadding |
static boolean |
hasPlacedAUnit |
private boolean |
isPlacementPhase |
private javafx.scene.paint.Paint |
movementHighlightColor |
private java.util.ArrayList<Move> |
movementList |
private boolean |
movementPhase |
private javafx.scene.control.Label |
phaseLabel |
private int |
phaseLabelHeight |
javafx.scene.layout.Pane |
phaseLabelPane |
private int |
phaseLabelYPadding |
private int |
placementButtonXPadding |
private int |
placementDescriptionYPadding |
private static javafx.scene.control.Label |
placeUnitLabel |
private java.lang.String |
placeUnitLabelBackgroundColor |
private int |
placeUnitLabelHeight |
private int |
placeUnitLabelWidth |
private static javafx.scene.layout.Pane |
placeUnitPane |
private static int |
playerSideSize |
private int |
recruitContentXPadding |
private static javafx.scene.layout.FlowPane |
recruitUnits |
private int |
recruitXPadding |
private int |
recruitYPadding |
private static javafx.scene.control.Label |
resourceLabel |
private static javafx.scene.layout.Pane |
root |
private int |
sidePanelContentXPadding |
private int |
sidePanelXPadding |
private int |
sidePanelYPadding |
private int |
surrenderButtonSpacing |
private int |
surrenderContentSpacing |
private boolean |
surrendered |
private int |
surrenderHeight |
private int |
surrenderWidth |
private int |
threadTimer |
private javafx.scene.control.Label |
turnCounter |
private int |
turnCounterXPadding |
private int |
turnCounterYPadding |
private UnitGenerator |
unitGenerator |
private static int |
unitPadding |
private boolean |
unitSelected |
private static int |
unitTilesWidth |
private int |
unitTilesYPadding |
private javafx.scene.paint.Paint |
untargetableTileColor |
private double |
windowHeight |
private double |
windowWidth |
| Constructor and Description |
|---|
GameMain() |
| Modifier and Type | Method and Description |
|---|---|
void |
actualSurrender()
This method is called upon by surrender() method, and this method
uses the method surrenderGame() from the Database Class to send information about
which player won, and increment games won for that player.
|
private void |
addObstacles()
Player 2 adds obstacles when he joins the game, this method calls upon the
method (GameLogic) game.createObstacles() which creates obstacles and give them a random placement
by using a Random number generator.Player 1 continuously wait and polls to check if obstacles have been added
before resuming the game flow of the program.
|
private void |
attack(javafx.scene.input.MouseEvent event)
Checks to see if in movementphase and if it's players turn, if it is then this method uses
getPosXFromEvent and getPosYFromEvent to get the MouseEvent.MouseClick transformed into
grid coordinates and uses the method getAttackableTiles() to get all pieces on tiles within attack
movement and uses checkForLegalAttack to see whether the piece player wants to attack is in the array of
attackable Tiles.
|
static void |
changeDescriptionLabel(java.lang.String newDescription,
java.lang.String newDescriptionHead)
Is a static method which sets the description used in the sidebar.
|
private void |
checkForGameOver()
Uses checkForEliminationVictory() method to see if opponent or player has pieces left on board, also checks the database
with the method db.checkForSurrencder() to check if opponent has surrendered.
|
private void |
clearHighLight()
Clear all fill from tiles in Grid.list.
|
private javafx.scene.layout.Pane |
createGrid()
Method for setting up different panes containing the UI elements.
|
private javafx.scene.layout.Pane |
createPhaseLabelPane()
Sets up a pane on the top of the game with a label to show status for turns,
phase info, etc.
|
private javafx.scene.layout.Pane |
createRecruitPane()
Creates a sidebar panel for placement phase, and adds the buttons, and Recruits to it.
|
private javafx.scene.layout.Pane |
createSidePanel()
Creates the sidepanel for the placement/movement/attack phase, and serves useful
for showing descriptions and buttons like Surrender and End Turn.
|
static void |
descriptionVisible(boolean visible)
Is a static method which controls if the description used in the sidebar is visible.
|
private void |
deselect()
Deselects the unit by resetting variables and change styling of tiles to go back to
default settings.
|
static void |
deselectRecruitTiles()
Deselects the other recruit tiles in the sidebar when selecting
another recruit tile.
|
private javafx.scene.shape.Path |
drawArrow(double startX,
double startY,
double endX,
double endY)
Creates an arrow path to be added by showPlaceUnitLabel() to illustrate how to add
units to the board.
|
private void |
endTurn()
If this method is called when it is players turn, then the turn integer increments,
and it changes the text labels to Waiting for other players.
|
private void |
gameCleanUp()
Resets all of the game variables so that if player wants to play another game, all the
data will be loaded on a new game.
|
private int |
getPosXFromEvent(javafx.scene.input.MouseEvent event)
Returns X-coordinates which corresponds with the Grid Class by using
MouseEvent.MouseClicked as argument and turns the pixel coordinates
to grid coordinates by rounding up to nearest tile size.
|
private int |
getPosYFromEvent(javafx.scene.input.MouseEvent event)
Returns Y-coordinates which corresponds with the Grid Class by using
MouseEvent.MouseClicked as argument and turns the pixel coordinates
to grid coordinates by rounding up to nearest tile size.
|
private void |
highlightPossibleAttacks()
Highlights all possible tiles that a unit can attack, by filling
tile with attack color.
|
private void |
highlightPossibleMoves()
Highlights all possible tiles that a unit can move, by filling
tile with with movement color.
|
private void |
importOpponentPlacementUnits()
Uses db.importPlacementUnits() method to import opponent's pieces onto board.
|
void |
main(java.lang.String[] args)
Calls for shutdown methods if program is closed.
|
private void |
move(javafx.scene.input.MouseEvent event)
If it is player's turn it gets mouseclick position from MouseEvent and uses
methods getPosYFromEvent() and getPosYFromEvent() to translate into x and y
coordinates corresponding with the grid/board.
|
private void |
movementPhaseStart()
Starts the movement phase, starts up creating panes for game with the methods
createSidePanel() and createPhaseLabelPane() to set up layouts for the game in
the movement phase.
|
private void |
placementPhaseFinished(javafx.scene.layout.Pane recruitPane)
When placement phase is finished, this method is called upon to remove the panes and
calls upon the method exportPlaceMentUnits() to export the position of the units placed in
the placement phase, and setReady() to indicate to the other player that opponent has finished placement
phase and is ready to start the game in Movement phase.
|
private void |
placementPhaseStart()
Starts the placement phase by setting variables currentResources = startingResources, calling upon
the method createRecruitPane() which enables Dragboard to work with recruit, recruit tiles,
and sets up a sidebar for display information like finishedPlacingButton, description, and sets up
the grid to be divided against the players, so that player 1 can place their units/recruits on the top
and player can place their units on the bottom.
|
static void |
removePlaceUnitLabel()
Method for removing placeUnitLabel and arrow after first unit is added to the board
|
private void |
select(javafx.scene.input.MouseEvent event)
Selects a unit, and depending on whether it is player's turn, or player unit, it does different actions.
|
private void |
setUpNewTurn()
Sets up the next turn by deselecting Units, incrementing turn counter, and changes the the text of
the button to "End Turn" instead of "Waiting for other player" and phase label to "Movement phase" instead of
"Waiting for other player".
|
private void |
showPlaceUnitLabel()
Adds a label to the board to communicate to the player to add units to the board.
|
void |
start(javafx.stage.Stage window)
Start is called upon whenever the application changes scenes.
|
void |
stop()
Executes when application shuts down.
|
private void |
surrender()
This method is called when a player hits the Surrender button.
|
static void |
updateResourceLabel()
It is a static method that updates the resource label, when called upon.
|
private void |
waitForOpponentReady()
Method for polling if opponent is finished with placement phase.
|
private void |
waitForTurn()
This method creates a new Thread which checks whose turn it is with the method
getTurnPlayer from Database Class and changes the static variable yourTurn=true
if method returns true.
|
private static final int playerSideSize
private static javafx.scene.layout.Pane root
private static final javafx.scene.control.Label description
private static final javafx.scene.control.Label descriptionHead
private static final javafx.scene.control.Label placeUnitLabel
private static final javafx.scene.control.Label resourceLabel
private final javafx.scene.control.Label turnCounter
private final javafx.scene.control.Label phaseLabel
private com.jfoenix.controls.JFXButton endTurnButton
private static javafx.scene.layout.FlowPane recruitUnits
public javafx.scene.layout.Pane phaseLabelPane
private static javafx.scene.layout.Pane placeUnitPane
private static javafx.scene.shape.Path arrow
private final double windowWidth
private final double windowHeight
private final int gameOverHeight
private final int gameOverWidth
private final int surrenderHeight
private final int surrenderWidth
private final int gameOverContentSpacing
private final int surrenderButtonSpacing
private final int surrenderContentSpacing
private final int buttonWidth
private final int buttonHeight
private final int phaseLabelHeight
private final int descriptionHeadHeigth
private final int placeUnitLabelWidth
private final int placeUnitLabelHeight
private static final int unitPadding
private static final int unitTilesWidth
private final int buttonYPadding
private final int buttonSpacing
private final int gridXPadding
private final int gridYPadding
private final int recruitXPadding
private final int recruitYPadding
private final int unitTilesYPadding
private final int placementDescriptionYPadding
private final int placementButtonXPadding
private final int recruitContentXPadding
private final int arrowWidth
private final int arrowHeadSize
private final int sidePanelXPadding
private final int sidePanelYPadding
private final int turnCounterXPadding
private final int turnCounterYPadding
private final int sidePanelContentXPadding
private final int descriptionYPadding
private final int descriptionXPadding
private final int phaseLabelYPadding
private boolean unitSelected
private java.util.ArrayList<Move> movementList
private java.util.ArrayList<Attack> attackList
private boolean movementPhase
private boolean isPlacementPhase
private boolean surrendered
private boolean gameFinished
public static boolean hasPlacedAUnit
private final int threadTimer
private UnitGenerator unitGenerator
private final java.lang.String arialFont
private final java.lang.String buttonBackgroundColor
private final java.lang.String fontSize32
private final java.lang.String descriptionHeadFontSize
private final javafx.scene.paint.Paint buttonTextColor
private final javafx.scene.paint.Paint movementHighlightColor
private final javafx.scene.paint.Paint attackHighlightColor
private final javafx.scene.paint.Paint untargetableTileColor
private final java.lang.String placeUnitLabelBackgroundColor
private final javafx.scene.paint.Paint arrowColor
private GameLogic game
public void start(javafx.stage.Stage window)
start
in class javafx.application.Application
GameLogic
,
Application
private void addObstacles()
private void placementPhaseStart()
public static void updateResourceLabel()
Variables
public static void deselectRecruitTiles()
Recruit
,
RecruitTile
private void placementPhaseFinished(javafx.scene.layout.Pane recruitPane)
recruitPane
- Takes in a PaneDatabase
,
Recruit
,
RecruitTile
private void waitForOpponentReady()
private void importOpponentPlacementUnits()
PiecePlacer
,
Grid
,
UnitGenerator
,
Database
private void movementPhaseStart()
GameLogic
private void move(javafx.scene.input.MouseEvent event)
event
- Takes in a MouseEvent.MouseClicked event.GameLogic
private void attack(javafx.scene.input.MouseEvent event)
private void highlightPossibleMoves()
GameLogic
private void highlightPossibleAttacks()
GameLogic
private void clearHighLight()
public static void changeDescriptionLabel(java.lang.String newDescription, java.lang.String newDescriptionHead)
newDescription
- Takes a String with the description that should show in the sidebar.newDescriptionHead
- Takes a String for the description head.Recruit
public static void descriptionVisible(boolean visible)
visible
- Takes a boolean to control whether the description and description head is visible or not.private void select(javafx.scene.input.MouseEvent event)
event
- Takes in a MouseEvent to use with getPosXFromEvent and getPosYFromEvent.private void deselect()
private int getPosXFromEvent(javafx.scene.input.MouseEvent event)
event
- Gets the coordinates from MouseEvent.MouseClicked.Grid
private int getPosYFromEvent(javafx.scene.input.MouseEvent event)
event
- Gets the coordinates from MouseEvent.MouseClicked.Grid
private void endTurn()
private void waitForTurn()
private void setUpNewTurn()
Database
private void surrender()
public void actualSurrender()
Database
private void checkForGameOver()
private void gameCleanUp()
private javafx.scene.layout.Pane createGrid()
Grid
private javafx.scene.layout.Pane createRecruitPane()
Recruit
,
RecruitTile
private void showPlaceUnitLabel()
public static void removePlaceUnitLabel()
Tile
private javafx.scene.shape.Path drawArrow(double startX, double startY, double endX, double endY)
startX
- double value for start x position of arrowstartY
- double value for start y position of arrowendX
- double value for end x position of arrowendY
- double value for end y position of arrowprivate javafx.scene.layout.Pane createSidePanel()
private javafx.scene.layout.Pane createPhaseLabelPane()
public void stop()
stop
in class javafx.application.Application
public void main(java.lang.String[] args)
args
- Takes in arguemnts for the main method.


# Mon Dec 21 21:55:59 2020 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: N-2018.03L-SP1-1 Install: C:\lscc\diamond\3.11_x64\synpbase OS: Windows 6.2 Hostname: VITTORIO Implementation : brainfuck_uP Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF284 : | Setting synthesis effort to medium for the design @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB) @N:MF284 : | Setting synthesis effort to medium for the design Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) @N:FA113 : brainfuck_up.v(79) | Pipelining module un1_pc[17:0]. For more information, search for "pipelining" in Online Help. @N:MF169 : brainfuck_up.v(78) | Pushed in register pc[17:0]. Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB) Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB) Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 151MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:01s 11.41ns 89 / 88 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 151MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. @A:BN291 : brainfuck_up.v(78) | Boundary register portRD.fb (in view: work.brainfuck_uP(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : brainfuck_up.v(78) | Boundary register portWR.fb (in view: work.brainfuck_uP(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : brainfuck_up.v(78) | Boundary register outPort_7_.fb (in view: work.brainfuck_uP(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : brainfuck_up.v(78) | Boundary register outPort_6_.fb (in view: work.brainfuck_uP(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : brainfuck_up.v(78) | Boundary register outPort_5_.fb (in view: work.brainfuck_uP(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : brainfuck_up.v(78) | Boundary register outPort_4_.fb (in view: work.brainfuck_uP(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : brainfuck_up.v(78) | Boundary register outPort_3_.fb (in view: work.brainfuck_uP(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : brainfuck_up.v(78) | Boundary register outPort_2_.fb (in view: work.brainfuck_uP(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : brainfuck_up.v(78) | Boundary register outPort_1_.fb (in view: work.brainfuck_uP(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : brainfuck_up.v(78) | Boundary register outPort_0_.fb (in view: work.brainfuck_uP(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : brainfuck_up.v(78) | Boundary register WR.fb (in view: work.brainfuck_uP(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : brainfuck_up.v(78) | Boundary register RD.fb (in view: work.brainfuck_uP(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 150MB peak: 151MB) Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 115MB peak: 151MB) Writing Analyst data base C:\Users\kuash\OneDrive\Documents\brainfuck\BrainFuck uP\bfuP 2020\Lattice Diamond Projects\v 1.0\brainfuck_uP\synwork\brainfuck_uP_brainfuck_uP_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 151MB) Writing EDIF Netlist and constraint files @N:FX1056 : | Writing EDF file: C:\Users\kuash\OneDrive\Documents\brainfuck\BrainFuck uP\bfuP 2020\Lattice Diamond Projects\v 1.0\brainfuck_uP\brainfuck_uP_brainfuck_uP.edi N-2018.03L-SP1-1 @N:BW106 : | Synplicity Constraint File capacitance units using default value of 1pF Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 153MB peak: 156MB) Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 153MB peak: 156MB) @W:MT420 : | Found inferred clock brainfuck_uP|bfup_clk with period 20.00ns. Please declare a user-defined clock on port bfup_clk. ##### START OF TIMING REPORT #####[ # Timing Report written on Mon Dec 21 21:56:02 2020 # Top view: brainfuck_uP Requested Frequency: 50.0 MHz Wire load mode: top Paths requested: 3 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 10.439 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------- brainfuck_uP|bfup_clk 50.0 MHz 104.6 MHz 20.000 9.561 10.439 inferred Inferred_clkgroup_0 ============================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------- brainfuck_uP|bfup_clk brainfuck_uP|bfup_clk | 20.000 10.439 | No paths - | No paths - | No paths - ===================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: brainfuck_uP|bfup_clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------ delay[0] brainfuck_uP|bfup_clk FD1S3IX Q delay[0] 1.108 10.439 delay[3] brainfuck_uP|bfup_clk FD1S3IX Q delay[3] 1.044 10.503 state[0] brainfuck_uP|bfup_clk FD1S3AY Q state[0] 1.276 11.391 delay[1] brainfuck_uP|bfup_clk FD1S3IX Q delay[1] 1.044 11.519 delay[2] brainfuck_uP|bfup_clk FD1S3JX Q delay[2] 1.044 11.519 delay[4] brainfuck_uP|bfup_clk FD1S3JX Q delay[4] 1.044 11.519 state[5] brainfuck_uP|bfup_clk FD1S3IX Q state[5] 1.188 12.129 brackets[0] brainfuck_uP|bfup_clk FD1S3IX Q brackets[0] 1.108 13.072 brackets[5] brainfuck_uP|bfup_clk FD1S3IX Q brackets[5] 1.044 13.136 brackets[8] brainfuck_uP|bfup_clk FD1S3IX Q brackets[8] 1.044 13.136 ================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------- acc_0io[7] brainfuck_uP|bfup_clk OFS1P3IX D acc_9[7] 20.089 10.439 brackets[17] brainfuck_uP|bfup_clk FD1S3IX D un1_brackets_17[17] 19.894 10.880 brackets[15] brainfuck_uP|bfup_clk FD1S3IX D un1_brackets_17[15] 19.894 11.023 brackets[16] brainfuck_uP|bfup_clk FD1S3IX D un1_brackets_17[16] 19.894 11.023 p[15] brainfuck_uP|bfup_clk FD1S3IX D un1_p_cry_15_0_S0 19.894 11.027 p[16] brainfuck_uP|bfup_clk FD1S3IX D un1_p_cry_15_0_S1 19.894 11.027 brackets[13] brainfuck_uP|bfup_clk FD1S3IX D un1_brackets_17[13] 19.894 11.166 brackets[14] brainfuck_uP|bfup_clk FD1S3IX D un1_brackets_17[14] 19.894 11.166 p[13] brainfuck_uP|bfup_clk FD1S3IX D un1_p_cry_13_0_S0 19.894 11.170 p[14] brainfuck_uP|bfup_clk FD1S3IX D un1_p_cry_13_0_S1 19.894 11.170 =========================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) = Required time: 20.089 - Propagation time: 9.650 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 10.439 Number of logic level(s): 8 Starting point: delay[0] / Q Ending point: acc_0io[7] / D The start point is clocked by brainfuck_uP|bfup_clk [rising] on pin CK The end point is clocked by brainfuck_uP|bfup_clk [rising] on pin SCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------- delay[0] FD1S3IX Q Out 1.108 1.108 - delay[0] Net - - - - 3 delay_RNIH8OL[3] ORCALUT4 A In 0.000 1.108 - delay_RNIH8OL[3] ORCALUT4 Z Out 1.017 2.125 - delay8_i_0_o2_1 Net - - - - 1 delay_RNITNCM1[1] ORCALUT4 A In 0.000 2.125 - delay_RNITNCM1[1] ORCALUT4 Z Out 1.329 3.453 - N_66 Net - - - - 21 acc_1_sqmuxa ORCALUT4 A In 0.000 3.453 - acc_1_sqmuxa ORCALUT4 Z Out 1.233 4.686 - acc_1_sqmuxa Net - - - - 6 pData_pad_RNIA3BI[2] ORCALUT4 A In 0.000 4.686 - pData_pad_RNIA3BI[2] ORCALUT4 Z Out 1.089 5.775 - CO2 Net - - - - 2 pData_pad_RNILLDC2[3] ORCALUT4 B In 0.000 5.775 - pData_pad_RNILLDC2[3] ORCALUT4 Z Out 1.153 6.928 - CO3 Net - - - - 3 pData_pad_RNIVJ3T2[5] ORCALUT4 A In 0.000 6.928 - pData_pad_RNIVJ3T2[5] ORCALUT4 Z Out 1.089 8.017 - CO5 Net - - - - 2 acc_9_RNO[7] ORCALUT4 A In 0.000 8.017 - acc_9_RNO[7] ORCALUT4 Z Out 1.017 9.033 - N_24 Net - - - - 1 acc_9[7] ORCALUT4 A In 0.000 9.033 - acc_9[7] ORCALUT4 Z Out 0.617 9.650 - acc_9[7] Net - - - - 1 acc_0io[7] OFS1P3IX D In 0.000 9.650 - ======================================================================================== Path information for path number 2: Requested Period: 20.000 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) = Required time: 20.089 - Propagation time: 9.586 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 10.503 Number of logic level(s): 8 Starting point: delay[3] / Q Ending point: acc_0io[7] / D The start point is clocked by brainfuck_uP|bfup_clk [rising] on pin CK The end point is clocked by brainfuck_uP|bfup_clk [rising] on pin SCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------- delay[3] FD1S3IX Q Out 1.044 1.044 - delay[3] Net - - - - 2 delay_RNIH8OL[3] ORCALUT4 B In 0.000 1.044 - delay_RNIH8OL[3] ORCALUT4 Z Out 1.017 2.061 - delay8_i_0_o2_1 Net - - - - 1 delay_RNITNCM1[1] ORCALUT4 A In 0.000 2.061 - delay_RNITNCM1[1] ORCALUT4 Z Out 1.329 3.389 - N_66 Net - - - - 21 acc_1_sqmuxa ORCALUT4 A In 0.000 3.389 - acc_1_sqmuxa ORCALUT4 Z Out 1.233 4.622 - acc_1_sqmuxa Net - - - - 6 pData_pad_RNIA3BI[2] ORCALUT4 A In 0.000 4.622 - pData_pad_RNIA3BI[2] ORCALUT4 Z Out 1.089 5.711 - CO2 Net - - - - 2 pData_pad_RNILLDC2[3] ORCALUT4 B In 0.000 5.711 - pData_pad_RNILLDC2[3] ORCALUT4 Z Out 1.153 6.864 - CO3 Net - - - - 3 pData_pad_RNIVJ3T2[5] ORCALUT4 A In 0.000 6.864 - pData_pad_RNIVJ3T2[5] ORCALUT4 Z Out 1.089 7.953 - CO5 Net - - - - 2 acc_9_RNO[7] ORCALUT4 A In 0.000 7.953 - acc_9_RNO[7] ORCALUT4 Z Out 1.017 8.969 - N_24 Net - - - - 1 acc_9[7] ORCALUT4 A In 0.000 8.969 - acc_9[7] ORCALUT4 Z Out 0.617 9.586 - acc_9[7] Net - - - - 1 acc_0io[7] OFS1P3IX D In 0.000 9.586 - ======================================================================================== Path information for path number 3: Requested Period: 20.000 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 19.894 - Propagation time: 9.014 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 10.880 Number of logic level(s): 13 Starting point: delay[0] / Q Ending point: brackets[17] / D The start point is clocked by brainfuck_uP|bfup_clk [rising] on pin CK The end point is clocked by brainfuck_uP|bfup_clk [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------- delay[0] FD1S3IX Q Out 1.108 1.108 - delay[0] Net - - - - 3 delay_RNIH8OL[3] ORCALUT4 A In 0.000 1.108 - delay_RNIH8OL[3] ORCALUT4 Z Out 1.017 2.125 - delay8_i_0_o2_1 Net - - - - 1 delay_RNITNCM1[1] ORCALUT4 A In 0.000 2.125 - delay_RNITNCM1[1] ORCALUT4 Z Out 1.329 3.453 - N_66 Net - - - - 21 un1_state_21 ORCALUT4 A In 0.000 3.453 - un1_state_21 ORCALUT4 Z Out 1.325 4.778 - un1_state_21 Net - - - - 20 un1_brackets_17_cry_0_0 CCU2D C1 In 0.000 4.778 - un1_brackets_17_cry_0_0 CCU2D COUT Out 1.544 6.323 - un1_brackets_17_cry_0 Net - - - - 1 un1_brackets_17_cry_1_0 CCU2D CIN In 0.000 6.323 - un1_brackets_17_cry_1_0 CCU2D COUT Out 0.143 6.465 - un1_brackets_17_cry_2 Net - - - - 1 un1_brackets_17_cry_3_0 CCU2D CIN In 0.000 6.465 - un1_brackets_17_cry_3_0 CCU2D COUT Out 0.143 6.608 - un1_brackets_17_cry_4 Net - - - - 1 un1_brackets_17_cry_5_0 CCU2D CIN In 0.000 6.608 - un1_brackets_17_cry_5_0 CCU2D COUT Out 0.143 6.751 - un1_brackets_17_cry_6 Net - - - - 1 un1_brackets_17_cry_7_0 CCU2D CIN In 0.000 6.751 - un1_brackets_17_cry_7_0 CCU2D COUT Out 0.143 6.894 - un1_brackets_17_cry_8 Net - - - - 1 un1_brackets_17_cry_9_0 CCU2D CIN In 0.000 6.894 - un1_brackets_17_cry_9_0 CCU2D COUT Out 0.143 7.037 - un1_brackets_17_cry_10 Net - - - - 1 un1_brackets_17_cry_11_0 CCU2D CIN In 0.000 7.037 - un1_brackets_17_cry_11_0 CCU2D COUT Out 0.143 7.179 - un1_brackets_17_cry_12 Net - - - - 1 un1_brackets_17_cry_13_0 CCU2D CIN In 0.000 7.179 - un1_brackets_17_cry_13_0 CCU2D COUT Out 0.143 7.322 - un1_brackets_17_cry_14 Net - - - - 1 un1_brackets_17_cry_15_0 CCU2D CIN In 0.000 7.322 - un1_brackets_17_cry_15_0 CCU2D COUT Out 0.143 7.465 - un1_brackets_17_cry_16 Net - - - - 1 un1_brackets_17_s_17_0 CCU2D CIN In 0.000 7.465 - un1_brackets_17_s_17_0 CCU2D S0 Out 1.549 9.014 - un1_brackets_17[17] Net - - - - 1 brackets[17] FD1S3IX D In 0.000 9.014 - =========================================================================================== ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 154MB peak: 156MB) Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 154MB peak: 156MB) --------------------------------------- Resource Usage Report Part: lcmxo2_640hc-4 Register bits: 88 of 640 (14%) PIC Latch: 0 I/O cells: 74 Details: BB: 8 CCU2D: 32 FD1P3IX: 1 FD1P3JX: 1 FD1S3AX: 1 FD1S3AY: 1 FD1S3IX: 61 FD1S3JX: 3 GSR: 1 IB: 19 INV: 2 OB: 29 OBZ: 18 OFS1P3IX: 17 OFS1P3JX: 3 ORCALUT4: 85 PUR: 1 VHI: 1 VLO: 1 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 34MB peak: 156MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Mon Dec 21 21:56:02 2020 ###########################################################]


Vertex Identification
Duck, duck, duck, goose.
What is a vertex?
A vertex is a point.
A cross-section of the ATLAS detector showing a vertex. The blue lines show the paths of found charged particles ("tracklets"). The yellow circles show the location of found vertices.


This is a form in which you answer some questions so that we can understand our users and consequently improve the website.


This is the test for basic functionality of heap snapshot view grid.
To use this test:
- load file in the browser;
- open DevTools (Ctrl+Shift+I on Win/Linux, Command+Option+I on Mac);
- go to 'Profiles' page;
- press 'Take heap snapshot' button
(eye icon on the left side of status bar);
On the left pane under 'Heap snapshots' section, an item called
'Snapshot 1' must appear, and a grid with snapshot data must
appear on the right. Now test the following functionality in the grid:
- change sorting order in each column by clicking on its header;
- resize each column;
- toggle between showing absolute times and percents
(button with percent sign on the status bar);
- double-click on numbers in 'Count' and
'Size' columns to toggle between times and percents for
this column only;
- expanding and collapsing tree nodes.


Refer to the links below for useful build documentation, generated from the Azure SDK for Java source code.


Home
JS Docs
Test
Readme Docs
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Type Without Ligatures
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Accordion 1
Panel 1. Lorem ipsum dolor
Accordion 2
Panel 2. Lorem ipsum dolor
Accordion 3
Panel 3. Lorem ipsum dolor


I don’t remember how I learned about Anil Dash, but I did and I was struck with the anecdote about why and how he started writing which apparently came out of a period of uncertainty. Uncertainty of what to do next, where to go. More on the relevance of that later. Since then I’ve wanted to back read his blog, but how does one go about getting all that content? I didn’t want to be restricted to reading it on iPadita’s data connection and Anil isn’t/wasn’t using a static site generator so downloading the repo was out of question.
Enter HTTrack, a free, relatively easy to use utility for scraping the web. ”It allows you to download a World Wide Web site from the Internet to a local directory, building recursively all directories, getting HTML, images, and other files from the server to your computer. HTTrack arranges the original site’s relative link-structure”
Download your flavor for you OS. If you’re on a mac run httrack -W
for simple prompt helper. Don’t let the verbose documentation or retro site scare you away. If you aren’t cataloging the whole internet, you’ll get exactly what you want with httrack -W
.
For more details on the options you can pass, start here, cmd + f
for A Thorough Going Over, and begin reading from there.
Happy Reading!
NB: This blog post lead me to HTTrack from this query.