Place & Route TRACE Report
Loading design for application trce from file ds18b20_impl1.ncd.
Design name: ds18b20_top
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-4000HC
Package: CSBGA132
Performance: 5
Loading device for application trce from file 'xo2c4000.nph' in environment: C:/lscc/diamond/3.10_x64/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond (64-bit) <IP_ADDRESS>.2
Fri Feb 19 19:37:54 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Command line: trce -v 10 -gt -sethld -sp 5 -sphld m -o ds18b20_impl1.twr -gui -msgset C:/fpga/ds18b20/promote.xml ds18b20_impl1.ncd ds18b20_impl1.prf
Design file: ds18b20_impl1.ncd
Preference file: ds18b20_impl1.prf
Device,speed: LCMXO2-4000HC,5
Report level: verbose report, limited to 10 items per preference
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Preference Summary
FREQUENCY NET "sys_clk_c" 103.756000 MHz (4096 errors)
4096 items scored, 4096 timing errors detected.
Warning: 4.805MHz is the maximum frequency for this preference.
FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz (4096 errors)
4096 items scored, 4096 timing errors detected.
Warning: 15.709MHz is the maximum frequency for this preference.
FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz (130 errors)
208 items scored, 130 timing errors detected.
Warning: 24.116MHz is the maximum frequency for this preference.
FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz (1027 errors)
1337 items scored, 1027 timing errors detected.
Warning: 5.268MHz is the maximum frequency for this preference.
FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz (1701 errors)
1998 items scored, 1701 timing errors detected.
Warning: 7.425MHz is the maximum frequency for this preference.
FREQUENCY NET "m_DS18B20Z/clk_1mhz" 293.858000 MHz (58 errors)
59 items scored, 58 timing errors detected.
Warning: 50.816MHz is the maximum frequency for this preference.
Report Type: based on TRACE automatically generated preferences
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY NET "sys_clk_c" 103.756000 MHz ;
4096 items scored, 4096 timing errors detected.
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Error: The following path exceeds requirements by 8.938ns (weighted slack = -198.490ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_high_i1 (from m_clock/clk_1ms +)
Destination: FF Data in m_OLED12832/char_i33 (to sys_clk_c +)
Delay: 6.153ns (36.0% logic, 64.0% route), 5 logic levels.
Constraint Details:
6.153ns physical path delay m_clock/SLICE_350 to m_OLED12832/SLICE_202 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 9.638ns)
0.434ns delay constraint less
3.069ns skew and
0.150ns DIN_SET requirement (totaling -2.785ns) by 8.938ns
Physical Path Details:
Data path m_clock/SLICE_350 to m_OLED12832/SLICE_202:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C20C.CLK to R18C20C.Q1 m_clock/SLICE_350 (from m_clock/clk_1ms)
ROUTE 14 1.055 R18C20C.Q1 to R19C23B.D0 time_hour_high_1
CTOF_DEL --- 0.452 R19C23B.D0 to R19C23B.F0 m_OLED12832/SLICE_919
ROUTE 1 1.953 R19C23B.F0 to R9C17C.D1 m_OLED12832/n17
CTOF_DEL --- 0.452 R9C17C.D1 to R9C17C.F1 m_OLED12832/SLICE_711
ROUTE 1 0.384 R9C17C.F1 to R9C17C.C0 m_OLED12832/char_167_N_690_33
CTOF_DEL --- 0.452 R9C17C.C0 to R9C17C.F0 m_OLED12832/SLICE_711
ROUTE 1 0.544 R9C17C.F0 to R9C17D.D0 m_OLED12832/n16_adj_1789
CTOF_DEL --- 0.452 R9C17D.D0 to R9C17D.F0 m_OLED12832/SLICE_202
ROUTE 1 0.000 R9C17D.F0 to R9C17D.DI0 m_OLED12832/char_167_N_359_33 (to sys_clk_c)
--------
6.153 (36.0% logic, 64.0% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_350:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R18C20C.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Destination Clock Path sys_clk to m_OLED12832/SLICE_202:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R9C17D.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Error: The following path exceeds requirements by 8.733ns (weighted slack = -193.937ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_low_i0 (from m_clock/clk_1ms +)
Destination: FF Data in m_OLED12832/char_i24 (to sys_clk_c +)
Delay: 5.948ns (37.3% logic, 62.7% route), 5 logic levels.
Constraint Details:
5.948ns physical path delay m_clock/SLICE_352 to m_OLED12832/SLICE_199 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 9.638ns)
0.434ns delay constraint less
3.069ns skew and
0.150ns DIN_SET requirement (totaling -2.785ns) by 8.733ns
Physical Path Details:
Data path m_clock/SLICE_352 to m_OLED12832/SLICE_199:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C19D.CLK to R20C19D.Q0 m_clock/SLICE_352 (from m_clock/clk_1ms)
ROUTE 19 1.010 R20C19D.Q0 to R19C18B.D0 time_hour_low_0
CTOF_DEL --- 0.452 R19C18B.D0 to R19C18B.F0 m_OLED12832/SLICE_960
ROUTE 1 1.953 R19C18B.F0 to R9C15B.D1 m_OLED12832/n17_adj_1869
CTOF_DEL --- 0.452 R9C15B.D1 to R9C15B.F1 m_OLED12832/SLICE_670
ROUTE 1 0.384 R9C15B.F1 to R9C15B.C0 m_OLED12832/char_167_N_690_24
CTOF_DEL --- 0.452 R9C15B.C0 to R9C15B.F0 m_OLED12832/SLICE_670
ROUTE 1 0.384 R9C15B.F0 to R9C15A.C0 m_OLED12832/n16_adj_1868
CTOF_DEL --- 0.452 R9C15A.C0 to R9C15A.F0 m_OLED12832/SLICE_199
ROUTE 1 0.000 R9C15A.F0 to R9C15A.DI0 m_OLED12832/char_167_N_359_24 (to sys_clk_c)
--------
5.948 (37.3% logic, 62.7% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_352:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C19D.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Destination Clock Path sys_clk to m_OLED12832/SLICE_199:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R9C15A.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Error: The following path exceeds requirements by 8.720ns (weighted slack = -193.648ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_high_i3 (from m_clock/clk_1ms +)
Destination: FF Data in m_OLED12832/char_i35 (to sys_clk_c +)
Delay: 5.935ns (37.4% logic, 62.6% route), 5 logic levels.
Constraint Details:
5.935ns physical path delay m_clock/SLICE_351 to m_OLED12832/SLICE_203 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 9.638ns)
0.434ns delay constraint less
3.069ns skew and
0.150ns DIN_SET requirement (totaling -2.785ns) by 8.720ns
Physical Path Details:
Data path m_clock/SLICE_351 to m_OLED12832/SLICE_203:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C20D.CLK to R18C20D.Q1 m_clock/SLICE_351 (from m_clock/clk_1ms)
ROUTE 7 1.045 R18C20D.Q1 to R19C23B.D1 time_hour_high_3
CTOF_DEL --- 0.452 R19C23B.D1 to R19C23B.F1 m_OLED12832/SLICE_919
ROUTE 1 1.745 R19C23B.F1 to R9C21D.D1 m_OLED12832/n17_adj_1693
CTOF_DEL --- 0.452 R9C21D.D1 to R9C21D.F1 m_OLED12832/SLICE_709
ROUTE 1 0.384 R9C21D.F1 to R9C21D.C0 m_OLED12832/char_167_N_690_35
CTOF_DEL --- 0.452 R9C21D.C0 to R9C21D.F0 m_OLED12832/SLICE_709
ROUTE 1 0.544 R9C21D.F0 to R9C21A.D0 m_OLED12832/n16_adj_1864
CTOF_DEL --- 0.452 R9C21A.D0 to R9C21A.F0 m_OLED12832/SLICE_203
ROUTE 1 0.000 R9C21A.F0 to R9C21A.DI0 m_OLED12832/char_167_N_359_35 (to sys_clk_c)
--------
5.935 (37.4% logic, 62.6% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_351:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R18C20D.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Destination Clock Path sys_clk to m_OLED12832/SLICE_203:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R9C21A.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Error: The following path exceeds requirements by 8.664ns (weighted slack = -192.405ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_min_high_i1 (from m_clock/clk_1ms +)
Destination: FF Data in m_OLED12832/char_i9 (to sys_clk_c +)
Delay: 5.879ns (37.7% logic, 62.3% route), 5 logic levels.
Constraint Details:
5.879ns physical path delay m_clock/SLICE_354 to m_OLED12832/SLICE_194 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 9.638ns)
0.434ns delay constraint less
3.069ns skew and
0.150ns DIN_SET requirement (totaling -2.785ns) by 8.664ns
Physical Path Details:
Data path m_clock/SLICE_354 to m_OLED12832/SLICE_194:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R19C20C.CLK to R19C20C.Q1 m_clock/SLICE_354 (from m_clock/clk_1ms)
ROUTE 18 0.877 R19C20C.Q1 to R19C18D.D1 time_min_high_1
CTOF_DEL --- 0.452 R19C18D.D1 to R19C18D.F1 m_OLED12832/SLICE_959
ROUTE 1 1.857 R19C18D.F1 to R9C16D.D1 m_OLED12832/n17_adj_1890
CTOF_DEL --- 0.452 R9C16D.D1 to R9C16D.F1 m_OLED12832/SLICE_714
ROUTE 1 0.384 R9C16D.F1 to R9C16D.C0 m_OLED12832/char_167_N_690_9
CTOF_DEL --- 0.452 R9C16D.C0 to R9C16D.F0 m_OLED12832/SLICE_714
ROUTE 1 0.544 R9C16D.F0 to R9C16B.D0 m_OLED12832/n16_adj_1889
CTOF_DEL --- 0.452 R9C16B.D0 to R9C16B.F0 m_OLED12832/SLICE_194
ROUTE 1 0.000 R9C16B.F0 to R9C16B.DI0 m_OLED12832/char_167_N_359_9 (to sys_clk_c)
--------
5.879 (37.7% logic, 62.3% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_354:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R19C20C.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Destination Clock Path sys_clk to m_OLED12832/SLICE_194:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R9C16B.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Error: The following path exceeds requirements by 8.654ns (weighted slack = -192.183ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_low_i3 (from m_clock/clk_1ms +)
Destination: FF Data in m_OLED12832/char_i27 (to sys_clk_c +)
Delay: 5.869ns (37.8% logic, 62.2% route), 5 logic levels.
Constraint Details:
5.869ns physical path delay m_clock/SLICE_353 to m_OLED12832/SLICE_200 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 9.638ns)
0.434ns delay constraint less
3.069ns skew and
0.150ns DIN_SET requirement (totaling -2.785ns) by 8.654ns
Physical Path Details:
Data path m_clock/SLICE_353 to m_OLED12832/SLICE_200:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C19A.CLK to R20C19A.Q1 m_clock/SLICE_353 (from m_clock/clk_1ms)
ROUTE 14 2.229 R20C19A.Q1 to R10C21C.B0 time_hour_low_3
CTOF_DEL --- 0.452 R10C21C.B0 to R10C21C.F0 m_OLED12832/SLICE_752
ROUTE 1 0.269 R10C21C.F0 to R10C21A.D1 m_OLED12832/n27531
CTOF_DEL --- 0.452 R10C21A.D1 to R10C21A.F1 m_OLED12832/SLICE_716
ROUTE 1 0.610 R10C21A.F1 to R10C21A.B0 m_OLED12832/char_167_N_690_27
CTOF_DEL --- 0.452 R10C21A.B0 to R10C21A.F0 m_OLED12832/SLICE_716
ROUTE 1 0.544 R10C21A.F0 to R10C21D.D1 m_OLED12832/n16_adj_1896
CTOF_DEL --- 0.452 R10C21D.D1 to R10C21D.F1 m_OLED12832/SLICE_200
ROUTE 1 0.000 R10C21D.F1 to R10C21D.DI1 m_OLED12832/char_167_N_359_27 (to sys_clk_c)
--------
5.869 (37.8% logic, 62.2% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_353:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C19A.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Destination Clock Path sys_clk to m_OLED12832/SLICE_200:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R10C21D.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Error: The following path exceeds requirements by 8.579ns (weighted slack = -190.517ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_min_low_i3 (from m_clock/clk_1ms +)
Destination: FF Data in m_OLED12832/char_i3 (to sys_clk_c +)
Delay: 5.794ns (41.9% logic, 58.1% route), 5 logic levels.
Constraint Details:
5.794ns physical path delay m_clock/SLICE_358 to m_OLED12832/SLICE_192 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 9.638ns)
0.434ns delay constraint less
3.069ns skew and
0.150ns DIN_SET requirement (totaling -2.785ns) by 8.579ns
Physical Path Details:
Data path m_clock/SLICE_358 to m_OLED12832/SLICE_192:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C23B.CLK to R20C23B.Q0 m_clock/SLICE_358 (from m_clock/clk_1ms)
ROUTE 11 1.605 R20C23B.Q0 to R15C20B.C1 time_min_low_3
CTOOFX_DEL --- 0.661 R15C20B.C1 to R15C20B.OFX0 m_OLED12832/i24294/SLICE_409
ROUTE 1 0.541 R15C20B.OFX0 to R16C20A.D1 m_OLED12832/n27213
CTOF_DEL --- 0.452 R16C20A.D1 to R16C20A.F1 m_OLED12832/SLICE_626
ROUTE 1 0.544 R16C20A.F1 to R16C20A.D0 m_OLED12832/char_167_N_690_3
CTOF_DEL --- 0.452 R16C20A.D0 to R16C20A.F0 m_OLED12832/SLICE_626
ROUTE 1 0.678 R16C20A.F0 to R16C18B.C1 m_OLED12832/n16_adj_1717
CTOF_DEL --- 0.452 R16C18B.C1 to R16C18B.F1 m_OLED12832/SLICE_192
ROUTE 1 0.000 R16C18B.F1 to R16C18B.DI1 m_OLED12832/char_167_N_359_3 (to sys_clk_c)
--------
5.794 (41.9% logic, 58.1% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_358:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C23B.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Destination Clock Path sys_clk to m_OLED12832/SLICE_192:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R16C18B.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Error: The following path exceeds requirements by 8.507ns (weighted slack = -188.918ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_min_low_i1 (from m_clock/clk_1ms +)
Destination: FF Data in m_uart2tone/alarm_cnt_2271__i2 (to sys_clk_c +)
FF m_uart2tone/alarm_cnt_2271__i1
Delay: 5.624ns (31.4% logic, 68.6% route), 4 logic levels.
Constraint Details:
5.624ns physical path delay m_clock/SLICE_356 to m_uart2tone/SLICE_66 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 9.638ns)
0.434ns delay constraint less
3.069ns skew and
0.248ns LSR_SET requirement (totaling -2.883ns) by 8.507ns
Physical Path Details:
Data path m_clock/SLICE_356 to m_uart2tone/SLICE_66:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C23C.CLK to R20C23C.Q1 m_clock/SLICE_356 (from m_clock/clk_1ms)
ROUTE 14 1.650 R20C23C.Q1 to R18C22C.A0 time_min_low_1
CTOF_DEL --- 0.452 R18C22C.A0 to R18C22C.F0 m_clock/SLICE_814
ROUTE 4 0.671 R18C22C.F0 to R18C23A.C1 n27680
CTOF_DEL --- 0.452 R18C23A.C1 to R18C23A.F1 SLICE_800
ROUTE 3 0.559 R18C23A.F1 to R18C23A.D0 n27562
CTOF_DEL --- 0.452 R18C23A.D0 to R18C23A.F0 SLICE_800
ROUTE 4 0.979 R18C23A.F0 to R18C24B.LSR m_uart2tone/n12411 (to sys_clk_c)
--------
5.624 (31.4% logic, 68.6% route), 4 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_356:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C23C.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Destination Clock Path sys_clk to m_uart2tone/SLICE_66:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R18C24B.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Error: The following path exceeds requirements by 8.507ns (weighted slack = -188.918ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_min_low_i1 (from m_clock/clk_1ms +)
Destination: FF Data in m_uart2tone/alarm_cnt_2271__i6 (to sys_clk_c +)
FF m_uart2tone/alarm_cnt_2271__i5
Delay: 5.624ns (31.4% logic, 68.6% route), 4 logic levels.
Constraint Details:
5.624ns physical path delay m_clock/SLICE_356 to m_uart2tone/SLICE_64 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 9.638ns)
0.434ns delay constraint less
3.069ns skew and
0.248ns LSR_SET requirement (totaling -2.883ns) by 8.507ns
Physical Path Details:
Data path m_clock/SLICE_356 to m_uart2tone/SLICE_64:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C23C.CLK to R20C23C.Q1 m_clock/SLICE_356 (from m_clock/clk_1ms)
ROUTE 14 1.650 R20C23C.Q1 to R18C22C.A0 time_min_low_1
CTOF_DEL --- 0.452 R18C22C.A0 to R18C22C.F0 m_clock/SLICE_814
ROUTE 4 0.671 R18C22C.F0 to R18C23A.C1 n27680
CTOF_DEL --- 0.452 R18C23A.C1 to R18C23A.F1 SLICE_800
ROUTE 3 0.559 R18C23A.F1 to R18C23A.D0 n27562
CTOF_DEL --- 0.452 R18C23A.D0 to R18C23A.F0 SLICE_800
ROUTE 4 0.979 R18C23A.F0 to R18C24D.LSR m_uart2tone/n12411 (to sys_clk_c)
--------
5.624 (31.4% logic, 68.6% route), 4 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_356:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C23C.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Destination Clock Path sys_clk to m_uart2tone/SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R18C24D.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Error: The following path exceeds requirements by 8.507ns (weighted slack = -188.918ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_min_low_i1 (from m_clock/clk_1ms +)
Destination: FF Data in m_uart2tone/alarm_cnt_2271__i4 (to sys_clk_c +)
FF m_uart2tone/alarm_cnt_2271__i3
Delay: 5.624ns (31.4% logic, 68.6% route), 4 logic levels.
Constraint Details:
5.624ns physical path delay m_clock/SLICE_356 to m_uart2tone/SLICE_65 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 9.638ns)
0.434ns delay constraint less
3.069ns skew and
0.248ns LSR_SET requirement (totaling -2.883ns) by 8.507ns
Physical Path Details:
Data path m_clock/SLICE_356 to m_uart2tone/SLICE_65:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C23C.CLK to R20C23C.Q1 m_clock/SLICE_356 (from m_clock/clk_1ms)
ROUTE 14 1.650 R20C23C.Q1 to R18C22C.A0 time_min_low_1
CTOF_DEL --- 0.452 R18C22C.A0 to R18C22C.F0 m_clock/SLICE_814
ROUTE 4 0.671 R18C22C.F0 to R18C23A.C1 n27680
CTOF_DEL --- 0.452 R18C23A.C1 to R18C23A.F1 SLICE_800
ROUTE 3 0.559 R18C23A.F1 to R18C23A.D0 n27562
CTOF_DEL --- 0.452 R18C23A.D0 to R18C23A.F0 SLICE_800
ROUTE 4 0.979 R18C23A.F0 to R18C24C.LSR m_uart2tone/n12411 (to sys_clk_c)
--------
5.624 (31.4% logic, 68.6% route), 4 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_356:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C23C.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Destination Clock Path sys_clk to m_uart2tone/SLICE_65:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R18C24C.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Error: The following path exceeds requirements by 8.507ns (weighted slack = -188.918ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_min_low_i1 (from m_clock/clk_1ms +)
Destination: FF Data in m_uart2tone/alarm_cnt_2271__i0 (to sys_clk_c +)
Delay: 5.624ns (31.4% logic, 68.6% route), 4 logic levels.
Constraint Details:
5.624ns physical path delay m_clock/SLICE_356 to m_uart2tone/SLICE_67 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 9.638ns)
0.434ns delay constraint less
3.069ns skew and
0.248ns LSR_SET requirement (totaling -2.883ns) by 8.507ns
Physical Path Details:
Data path m_clock/SLICE_356 to m_uart2tone/SLICE_67:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C23C.CLK to R20C23C.Q1 m_clock/SLICE_356 (from m_clock/clk_1ms)
ROUTE 14 1.650 R20C23C.Q1 to R18C22C.A0 time_min_low_1
CTOF_DEL --- 0.452 R18C22C.A0 to R18C22C.F0 m_clock/SLICE_814
ROUTE 4 0.671 R18C22C.F0 to R18C23A.C1 n27680
CTOF_DEL --- 0.452 R18C23A.C1 to R18C23A.F1 SLICE_800
ROUTE 3 0.559 R18C23A.F1 to R18C23A.D0 n27562
CTOF_DEL --- 0.452 R18C23A.D0 to R18C23A.F0 SLICE_800
ROUTE 4 0.979 R18C23A.F0 to R18C24A.LSR m_uart2tone/n12411 (to sys_clk_c)
--------
5.624 (31.4% logic, 68.6% route), 4 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_356:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C23C.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Destination Clock Path sys_clk to m_uart2tone/SLICE_67:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R18C24A.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Warning: 4.805MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ;
4096 items scored, 4096 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 11.431ns (weighted slack = -54.798ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i7 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i2 (to m_uart_tx/clk_en +)
FF m_uart_tx/uart_data_i1
Delay: 17.067ns (26.2% logic, 73.8% route), 10 logic levels.
Constraint Details:
17.067ns physical path delay SLICE_347 to SLICE_319 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
1.848ns delay constraint less
-4.036ns skew and
0.248ns LSR_SET requirement (totaling 5.636ns) by 11.431ns
Physical Path Details:
Data path SLICE_347 to SLICE_319:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C14A.CLK to R18C14A.Q1 SLICE_347 (from sys_clk_c)
ROUTE 17 1.524 R18C14A.Q1 to R16C14B.C1 temp_raw_data_7
CTOF_DEL --- 0.452 R16C14B.C1 to R16C14B.F1 m_bcd_8421/SLICE_829
ROUTE 6 1.357 R16C14B.F1 to R16C15A.D1 m_bcd_8421/n27684
CTOF_DEL --- 0.452 R16C15A.D1 to R16C15A.F1 m_bcd_8421/SLICE_833
ROUTE 1 0.882 R16C15A.F1 to R16C14A.B1 m_bcd_8421/n17629
CTOF_DEL --- 0.452 R16C14A.B1 to R16C14A.F1 m_bcd_8421/SLICE_837
ROUTE 2 1.163 R16C14A.F1 to R16C17C.A1 m_bcd_8421/n25255
CTOF_DEL --- 0.452 R16C17C.A1 to R16C17C.F1 m_bcd_8421/SLICE_830
ROUTE 1 0.854 R16C17C.F1 to R16C17A.A1 m_bcd_8421/n6_adj_1656
CTOF_DEL --- 0.452 R16C17A.A1 to R16C17A.F1 SLICE_334
ROUTE 4 0.925 R16C17A.F1 to R17C17B.B1 n25294
CTOF_DEL --- 0.452 R17C17B.B1 to R17C17B.F1 SLICE_319
ROUTE 4 1.619 R17C17B.F1 to R16C17B.D0 n27541
CTOF_DEL --- 0.452 R16C17B.D0 to R16C17B.F0 SLICE_616
ROUTE 1 0.384 R16C17B.F0 to R16C17B.C1 m_uart_tx/n4
CTOF_DEL --- 0.452 R16C17B.C1 to R16C17B.F1 SLICE_616
ROUTE 3 0.888 R16C17B.F1 to R17C17D.A0 n26544
CTOF_DEL --- 0.452 R17C17D.A0 to R17C17D.F0 SLICE_329
ROUTE 14 2.994 R17C17D.F0 to R17C17B.LSR uart_data_120_N_1005_5 (to m_uart_tx/clk_en)
--------
17.067 (26.2% logic, 73.8% route), 10 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_347:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R18C14A.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Destination Clock Path sys_clk to SLICE_319:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.409 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 3.627 R12C11D.Q0 to R17C17B.CLK m_uart_tx/clk_en
--------
7.958 (19.4% logic, 80.6% route), 2 logic levels.
Error: The following path exceeds requirements by 11.431ns (weighted slack = -54.798ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i7 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i7 (to m_uart_tx/clk_en +)
FF m_uart_tx/uart_data_i6
Delay: 17.067ns (26.2% logic, 73.8% route), 10 logic levels.
Constraint Details:
17.067ns physical path delay SLICE_347 to SLICE_320 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
1.848ns delay constraint less
-4.036ns skew and
0.248ns LSR_SET requirement (totaling 5.636ns) by 11.431ns
Physical Path Details:
Data path SLICE_347 to SLICE_320:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C14A.CLK to R18C14A.Q1 SLICE_347 (from sys_clk_c)
ROUTE 17 1.524 R18C14A.Q1 to R16C14B.C1 temp_raw_data_7
CTOF_DEL --- 0.452 R16C14B.C1 to R16C14B.F1 m_bcd_8421/SLICE_829
ROUTE 6 1.357 R16C14B.F1 to R16C15A.D1 m_bcd_8421/n27684
CTOF_DEL --- 0.452 R16C15A.D1 to R16C15A.F1 m_bcd_8421/SLICE_833
ROUTE 1 0.882 R16C15A.F1 to R16C14A.B1 m_bcd_8421/n17629
CTOF_DEL --- 0.452 R16C14A.B1 to R16C14A.F1 m_bcd_8421/SLICE_837
ROUTE 2 1.163 R16C14A.F1 to R16C17C.A1 m_bcd_8421/n25255
CTOF_DEL --- 0.452 R16C17C.A1 to R16C17C.F1 m_bcd_8421/SLICE_830
ROUTE 1 0.854 R16C17C.F1 to R16C17A.A1 m_bcd_8421/n6_adj_1656
CTOF_DEL --- 0.452 R16C17A.A1 to R16C17A.F1 SLICE_334
ROUTE 4 0.925 R16C17A.F1 to R17C17B.B1 n25294
CTOF_DEL --- 0.452 R17C17B.B1 to R17C17B.F1 SLICE_319
ROUTE 4 1.619 R17C17B.F1 to R16C17B.D0 n27541
CTOF_DEL --- 0.452 R16C17B.D0 to R16C17B.F0 SLICE_616
ROUTE 1 0.384 R16C17B.F0 to R16C17B.C1 m_uart_tx/n4
CTOF_DEL --- 0.452 R16C17B.C1 to R16C17B.F1 SLICE_616
ROUTE 3 0.888 R16C17B.F1 to R17C17D.A0 n26544
CTOF_DEL --- 0.452 R17C17D.A0 to R17C17D.F0 SLICE_329
ROUTE 14 2.994 R17C17D.F0 to R16C15C.LSR uart_data_120_N_1005_5 (to m_uart_tx/clk_en)
--------
17.067 (26.2% logic, 73.8% route), 10 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_347:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R18C14A.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Destination Clock Path sys_clk to SLICE_320:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.409 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 3.627 R12C11D.Q0 to R16C15C.CLK m_uart_tx/clk_en
--------
7.958 (19.4% logic, 80.6% route), 2 logic levels.
Error: The following path exceeds requirements by 11.431ns (weighted slack = -54.798ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i7 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i9 (to m_uart_tx/clk_en +)
FF m_uart_tx/uart_data_i8
Delay: 17.067ns (26.2% logic, 73.8% route), 10 logic levels.
Constraint Details:
17.067ns physical path delay SLICE_347 to SLICE_321 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
1.848ns delay constraint less
-4.036ns skew and
0.248ns LSR_SET requirement (totaling 5.636ns) by 11.431ns
Physical Path Details:
Data path SLICE_347 to SLICE_321:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C14A.CLK to R18C14A.Q1 SLICE_347 (from sys_clk_c)
ROUTE 17 1.524 R18C14A.Q1 to R16C14B.C1 temp_raw_data_7
CTOF_DEL --- 0.452 R16C14B.C1 to R16C14B.F1 m_bcd_8421/SLICE_829
ROUTE 6 1.357 R16C14B.F1 to R16C15A.D1 m_bcd_8421/n27684
CTOF_DEL --- 0.452 R16C15A.D1 to R16C15A.F1 m_bcd_8421/SLICE_833
ROUTE 1 0.882 R16C15A.F1 to R16C14A.B1 m_bcd_8421/n17629
CTOF_DEL --- 0.452 R16C14A.B1 to R16C14A.F1 m_bcd_8421/SLICE_837
ROUTE 2 1.163 R16C14A.F1 to R16C17C.A1 m_bcd_8421/n25255
CTOF_DEL --- 0.452 R16C17C.A1 to R16C17C.F1 m_bcd_8421/SLICE_830
ROUTE 1 0.854 R16C17C.F1 to R16C17A.A1 m_bcd_8421/n6_adj_1656
CTOF_DEL --- 0.452 R16C17A.A1 to R16C17A.F1 SLICE_334
ROUTE 4 0.925 R16C17A.F1 to R17C17B.B1 n25294
CTOF_DEL --- 0.452 R17C17B.B1 to R17C17B.F1 SLICE_319
ROUTE 4 1.619 R17C17B.F1 to R16C17B.D0 n27541
CTOF_DEL --- 0.452 R16C17B.D0 to R16C17B.F0 SLICE_616
ROUTE 1 0.384 R16C17B.F0 to R16C17B.C1 m_uart_tx/n4
CTOF_DEL --- 0.452 R16C17B.C1 to R16C17B.F1 SLICE_616
ROUTE 3 0.888 R16C17B.F1 to R17C17D.A0 n26544
CTOF_DEL --- 0.452 R17C17D.A0 to R17C17D.F0 SLICE_329
ROUTE 14 2.994 R17C17D.F0 to R18C17A.LSR uart_data_120_N_1005_5 (to m_uart_tx/clk_en)
--------
17.067 (26.2% logic, 73.8% route), 10 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_347:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R18C14A.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Destination Clock Path sys_clk to SLICE_321:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.409 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 3.627 R12C11D.Q0 to R18C17A.CLK m_uart_tx/clk_en
--------
7.958 (19.4% logic, 80.6% route), 2 logic levels.
Error: The following path exceeds requirements by 11.431ns (weighted slack = -54.798ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i7 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i16 (to m_uart_tx/clk_en +)
FF m_uart_tx/uart_data_i15
Delay: 17.067ns (26.2% logic, 73.8% route), 10 logic levels.
Constraint Details:
17.067ns physical path delay SLICE_347 to SLICE_322 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
1.848ns delay constraint less
-4.036ns skew and
0.248ns LSR_SET requirement (totaling 5.636ns) by 11.431ns
Physical Path Details:
Data path SLICE_347 to SLICE_322:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C14A.CLK to R18C14A.Q1 SLICE_347 (from sys_clk_c)
ROUTE 17 1.524 R18C14A.Q1 to R16C14B.C1 temp_raw_data_7
CTOF_DEL --- 0.452 R16C14B.C1 to R16C14B.F1 m_bcd_8421/SLICE_829
ROUTE 6 1.357 R16C14B.F1 to R16C15A.D1 m_bcd_8421/n27684
CTOF_DEL --- 0.452 R16C15A.D1 to R16C15A.F1 m_bcd_8421/SLICE_833
ROUTE 1 0.882 R16C15A.F1 to R16C14A.B1 m_bcd_8421/n17629
CTOF_DEL --- 0.452 R16C14A.B1 to R16C14A.F1 m_bcd_8421/SLICE_837
ROUTE 2 1.163 R16C14A.F1 to R16C17C.A1 m_bcd_8421/n25255
CTOF_DEL --- 0.452 R16C17C.A1 to R16C17C.F1 m_bcd_8421/SLICE_830
ROUTE 1 0.854 R16C17C.F1 to R16C17A.A1 m_bcd_8421/n6_adj_1656
CTOF_DEL --- 0.452 R16C17A.A1 to R16C17A.F1 SLICE_334
ROUTE 4 0.925 R16C17A.F1 to R17C17B.B1 n25294
CTOF_DEL --- 0.452 R17C17B.B1 to R17C17B.F1 SLICE_319
ROUTE 4 1.619 R17C17B.F1 to R16C17B.D0 n27541
CTOF_DEL --- 0.452 R16C17B.D0 to R16C17B.F0 SLICE_616
ROUTE 1 0.384 R16C17B.F0 to R16C17B.C1 m_uart_tx/n4
CTOF_DEL --- 0.452 R16C17B.C1 to R16C17B.F1 SLICE_616
ROUTE 3 0.888 R16C17B.F1 to R17C17D.A0 n26544
CTOF_DEL --- 0.452 R17C17D.A0 to R17C17D.F0 SLICE_329
ROUTE 14 2.994 R17C17D.F0 to R17C18A.LSR uart_data_120_N_1005_5 (to m_uart_tx/clk_en)
--------
17.067 (26.2% logic, 73.8% route), 10 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_347:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R18C14A.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Destination Clock Path sys_clk to SLICE_322:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.409 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 3.627 R12C11D.Q0 to R17C18A.CLK m_uart_tx/clk_en
--------
7.958 (19.4% logic, 80.6% route), 2 logic levels.
Error: The following path exceeds requirements by 11.431ns (weighted slack = -54.798ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i7 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i17 (to m_uart_tx/clk_en +)
Delay: 17.067ns (26.2% logic, 73.8% route), 10 logic levels.
Constraint Details:
17.067ns physical path delay SLICE_347 to SLICE_323 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
1.848ns delay constraint less
-4.036ns skew and
0.248ns LSR_SET requirement (totaling 5.636ns) by 11.431ns
Physical Path Details:
Data path SLICE_347 to SLICE_323:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C14A.CLK to R18C14A.Q1 SLICE_347 (from sys_clk_c)
ROUTE 17 1.524 R18C14A.Q1 to R16C14B.C1 temp_raw_data_7
CTOF_DEL --- 0.452 R16C14B.C1 to R16C14B.F1 m_bcd_8421/SLICE_829
ROUTE 6 1.357 R16C14B.F1 to R16C15A.D1 m_bcd_8421/n27684
CTOF_DEL --- 0.452 R16C15A.D1 to R16C15A.F1 m_bcd_8421/SLICE_833
ROUTE 1 0.882 R16C15A.F1 to R16C14A.B1 m_bcd_8421/n17629
CTOF_DEL --- 0.452 R16C14A.B1 to R16C14A.F1 m_bcd_8421/SLICE_837
ROUTE 2 1.163 R16C14A.F1 to R16C17C.A1 m_bcd_8421/n25255
CTOF_DEL --- 0.452 R16C17C.A1 to R16C17C.F1 m_bcd_8421/SLICE_830
ROUTE 1 0.854 R16C17C.F1 to R16C17A.A1 m_bcd_8421/n6_adj_1656
CTOF_DEL --- 0.452 R16C17A.A1 to R16C17A.F1 SLICE_334
ROUTE 4 0.925 R16C17A.F1 to R17C17B.B1 n25294
CTOF_DEL --- 0.452 R17C17B.B1 to R17C17B.F1 SLICE_319
ROUTE 4 1.619 R17C17B.F1 to R16C17B.D0 n27541
CTOF_DEL --- 0.452 R16C17B.D0 to R16C17B.F0 SLICE_616
ROUTE 1 0.384 R16C17B.F0 to R16C17B.C1 m_uart_tx/n4
CTOF_DEL --- 0.452 R16C17B.C1 to R16C17B.F1 SLICE_616
ROUTE 3 0.888 R16C17B.F1 to R17C17D.A0 n26544
CTOF_DEL --- 0.452 R17C17D.A0 to R17C17D.F0 SLICE_329
ROUTE 14 2.994 R17C17D.F0 to R17C19A.LSR uart_data_120_N_1005_5 (to m_uart_tx/clk_en)
--------
17.067 (26.2% logic, 73.8% route), 10 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_347:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R18C14A.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Destination Clock Path sys_clk to SLICE_323:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.409 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 3.627 R12C11D.Q0 to R17C19A.CLK m_uart_tx/clk_en
--------
7.958 (19.4% logic, 80.6% route), 2 logic levels.
Error: The following path exceeds requirements by 11.431ns (weighted slack = -54.798ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i7 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i48 (to m_uart_tx/clk_en +)
FF m_uart_tx/uart_data_i47
Delay: 17.067ns (26.2% logic, 73.8% route), 10 logic levels.
Constraint Details:
17.067ns physical path delay SLICE_347 to SLICE_615 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
1.848ns delay constraint less
-4.036ns skew and
0.248ns LSR_SET requirement (totaling 5.636ns) by 11.431ns
Physical Path Details:
Data path SLICE_347 to SLICE_615:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C14A.CLK to R18C14A.Q1 SLICE_347 (from sys_clk_c)
ROUTE 17 1.524 R18C14A.Q1 to R16C14B.C1 temp_raw_data_7
CTOF_DEL --- 0.452 R16C14B.C1 to R16C14B.F1 m_bcd_8421/SLICE_829
ROUTE 6 1.357 R16C14B.F1 to R16C15A.D1 m_bcd_8421/n27684
CTOF_DEL --- 0.452 R16C15A.D1 to R16C15A.F1 m_bcd_8421/SLICE_833
ROUTE 1 0.882 R16C15A.F1 to R16C14A.B1 m_bcd_8421/n17629
CTOF_DEL --- 0.452 R16C14A.B1 to R16C14A.F1 m_bcd_8421/SLICE_837
ROUTE 2 1.163 R16C14A.F1 to R16C17C.A1 m_bcd_8421/n25255
CTOF_DEL --- 0.452 R16C17C.A1 to R16C17C.F1 m_bcd_8421/SLICE_830
ROUTE 1 0.854 R16C17C.F1 to R16C17A.A1 m_bcd_8421/n6_adj_1656
CTOF_DEL --- 0.452 R16C17A.A1 to R16C17A.F1 SLICE_334
ROUTE 4 0.925 R16C17A.F1 to R17C17B.B1 n25294
CTOF_DEL --- 0.452 R17C17B.B1 to R17C17B.F1 SLICE_319
ROUTE 4 1.619 R17C17B.F1 to R16C17B.D0 n27541
CTOF_DEL --- 0.452 R16C17B.D0 to R16C17B.F0 SLICE_616
ROUTE 1 0.384 R16C17B.F0 to R16C17B.C1 m_uart_tx/n4
CTOF_DEL --- 0.452 R16C17B.C1 to R16C17B.F1 SLICE_616
ROUTE 3 0.888 R16C17B.F1 to R17C17D.A0 n26544
CTOF_DEL --- 0.452 R17C17D.A0 to R17C17D.F0 SLICE_329
ROUTE 14 2.994 R17C17D.F0 to R17C19C.LSR uart_data_120_N_1005_5 (to m_uart_tx/clk_en)
--------
17.067 (26.2% logic, 73.8% route), 10 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_347:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R18C14A.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Destination Clock Path sys_clk to SLICE_615:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.409 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 3.627 R12C11D.Q0 to R17C19C.CLK m_uart_tx/clk_en
--------
7.958 (19.4% logic, 80.6% route), 2 logic levels.
Error: The following path exceeds requirements by 11.431ns (weighted slack = -54.798ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i7 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i27 (to m_uart_tx/clk_en +)
FF m_uart_tx/uart_data_i26
Delay: 17.067ns (26.2% logic, 73.8% route), 10 logic levels.
Constraint Details:
17.067ns physical path delay SLICE_347 to SLICE_733 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
1.848ns delay constraint less
-4.036ns skew and
0.248ns LSR_SET requirement (totaling 5.636ns) by 11.431ns
Physical Path Details:
Data path SLICE_347 to SLICE_733:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C14A.CLK to R18C14A.Q1 SLICE_347 (from sys_clk_c)
ROUTE 17 1.524 R18C14A.Q1 to R16C14B.C1 temp_raw_data_7
CTOF_DEL --- 0.452 R16C14B.C1 to R16C14B.F1 m_bcd_8421/SLICE_829
ROUTE 6 1.357 R16C14B.F1 to R16C15A.D1 m_bcd_8421/n27684
CTOF_DEL --- 0.452 R16C15A.D1 to R16C15A.F1 m_bcd_8421/SLICE_833
ROUTE 1 0.882 R16C15A.F1 to R16C14A.B1 m_bcd_8421/n17629
CTOF_DEL --- 0.452 R16C14A.B1 to R16C14A.F1 m_bcd_8421/SLICE_837
ROUTE 2 1.163 R16C14A.F1 to R16C17C.A1 m_bcd_8421/n25255
CTOF_DEL --- 0.452 R16C17C.A1 to R16C17C.F1 m_bcd_8421/SLICE_830
ROUTE 1 0.854 R16C17C.F1 to R16C17A.A1 m_bcd_8421/n6_adj_1656
CTOF_DEL --- 0.452 R16C17A.A1 to R16C17A.F1 SLICE_334
ROUTE 4 0.925 R16C17A.F1 to R17C17B.B1 n25294
CTOF_DEL --- 0.452 R17C17B.B1 to R17C17B.F1 SLICE_319
ROUTE 4 1.619 R17C17B.F1 to R16C17B.D0 n27541
CTOF_DEL --- 0.452 R16C17B.D0 to R16C17B.F0 SLICE_616
ROUTE 1 0.384 R16C17B.F0 to R16C17B.C1 m_uart_tx/n4
CTOF_DEL --- 0.452 R16C17B.C1 to R16C17B.F1 SLICE_616
ROUTE 3 0.888 R16C17B.F1 to R17C17D.A0 n26544
CTOF_DEL --- 0.452 R17C17D.A0 to R17C17D.F0 SLICE_329
ROUTE 14 2.994 R17C17D.F0 to R17C18C.LSR uart_data_120_N_1005_5 (to m_uart_tx/clk_en)
--------
17.067 (26.2% logic, 73.8% route), 10 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_347:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R18C14A.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Destination Clock Path sys_clk to SLICE_733:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.409 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 3.627 R12C11D.Q0 to R17C18C.CLK m_uart_tx/clk_en
--------
7.958 (19.4% logic, 80.6% route), 2 logic levels.
Error: The following path exceeds requirements by 11.431ns (weighted slack = -54.798ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i7 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i46 (to m_uart_tx/clk_en +)
FF m_uart_tx/uart_data_i45
Delay: 17.067ns (26.2% logic, 73.8% route), 10 logic levels.
Constraint Details:
17.067ns physical path delay SLICE_347 to SLICE_734 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
1.848ns delay constraint less
-4.036ns skew and
0.248ns LSR_SET requirement (totaling 5.636ns) by 11.431ns
Physical Path Details:
Data path SLICE_347 to SLICE_734:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C14A.CLK to R18C14A.Q1 SLICE_347 (from sys_clk_c)
ROUTE 17 1.524 R18C14A.Q1 to R16C14B.C1 temp_raw_data_7
CTOF_DEL --- 0.452 R16C14B.C1 to R16C14B.F1 m_bcd_8421/SLICE_829
ROUTE 6 1.357 R16C14B.F1 to R16C15A.D1 m_bcd_8421/n27684
CTOF_DEL --- 0.452 R16C15A.D1 to R16C15A.F1 m_bcd_8421/SLICE_833
ROUTE 1 0.882 R16C15A.F1 to R16C14A.B1 m_bcd_8421/n17629
CTOF_DEL --- 0.452 R16C14A.B1 to R16C14A.F1 m_bcd_8421/SLICE_837
ROUTE 2 1.163 R16C14A.F1 to R16C17C.A1 m_bcd_8421/n25255
CTOF_DEL --- 0.452 R16C17C.A1 to R16C17C.F1 m_bcd_8421/SLICE_830
ROUTE 1 0.854 R16C17C.F1 to R16C17A.A1 m_bcd_8421/n6_adj_1656
CTOF_DEL --- 0.452 R16C17A.A1 to R16C17A.F1 SLICE_334
ROUTE 4 0.925 R16C17A.F1 to R17C17B.B1 n25294
CTOF_DEL --- 0.452 R17C17B.B1 to R17C17B.F1 SLICE_319
ROUTE 4 1.619 R17C17B.F1 to R16C17B.D0 n27541
CTOF_DEL --- 0.452 R16C17B.D0 to R16C17B.F0 SLICE_616
ROUTE 1 0.384 R16C17B.F0 to R16C17B.C1 m_uart_tx/n4
CTOF_DEL --- 0.452 R16C17B.C1 to R16C17B.F1 SLICE_616
ROUTE 3 0.888 R16C17B.F1 to R17C17D.A0 n26544
CTOF_DEL --- 0.452 R17C17D.A0 to R17C17D.F0 SLICE_329
ROUTE 14 2.994 R17C17D.F0 to R17C20A.LSR uart_data_120_N_1005_5 (to m_uart_tx/clk_en)
--------
17.067 (26.2% logic, 73.8% route), 10 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_347:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R18C14A.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Destination Clock Path sys_clk to SLICE_734:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.409 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 3.627 R12C11D.Q0 to R17C20A.CLK m_uart_tx/clk_en
--------
7.958 (19.4% logic, 80.6% route), 2 logic levels.
Error: The following path exceeds requirements by 11.431ns (weighted slack = -54.798ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i7 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i41 (to m_uart_tx/clk_en +)
FF m_uart_tx/uart_data_i40
Delay: 17.067ns (26.2% logic, 73.8% route), 10 logic levels.
Constraint Details:
17.067ns physical path delay SLICE_347 to SLICE_735 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
1.848ns delay constraint less
-4.036ns skew and
0.248ns LSR_SET requirement (totaling 5.636ns) by 11.431ns
Physical Path Details:
Data path SLICE_347 to SLICE_735:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C14A.CLK to R18C14A.Q1 SLICE_347 (from sys_clk_c)
ROUTE 17 1.524 R18C14A.Q1 to R16C14B.C1 temp_raw_data_7
CTOF_DEL --- 0.452 R16C14B.C1 to R16C14B.F1 m_bcd_8421/SLICE_829
ROUTE 6 1.357 R16C14B.F1 to R16C15A.D1 m_bcd_8421/n27684
CTOF_DEL --- 0.452 R16C15A.D1 to R16C15A.F1 m_bcd_8421/SLICE_833
ROUTE 1 0.882 R16C15A.F1 to R16C14A.B1 m_bcd_8421/n17629
CTOF_DEL --- 0.452 R16C14A.B1 to R16C14A.F1 m_bcd_8421/SLICE_837
ROUTE 2 1.163 R16C14A.F1 to R16C17C.A1 m_bcd_8421/n25255
CTOF_DEL --- 0.452 R16C17C.A1 to R16C17C.F1 m_bcd_8421/SLICE_830
ROUTE 1 0.854 R16C17C.F1 to R16C17A.A1 m_bcd_8421/n6_adj_1656
CTOF_DEL --- 0.452 R16C17A.A1 to R16C17A.F1 SLICE_334
ROUTE 4 0.925 R16C17A.F1 to R17C17B.B1 n25294
CTOF_DEL --- 0.452 R17C17B.B1 to R17C17B.F1 SLICE_319
ROUTE 4 1.619 R17C17B.F1 to R16C17B.D0 n27541
CTOF_DEL --- 0.452 R16C17B.D0 to R16C17B.F0 SLICE_616
ROUTE 1 0.384 R16C17B.F0 to R16C17B.C1 m_uart_tx/n4
CTOF_DEL --- 0.452 R16C17B.C1 to R16C17B.F1 SLICE_616
ROUTE 3 0.888 R16C17B.F1 to R17C17D.A0 n26544
CTOF_DEL --- 0.452 R17C17D.A0 to R17C17D.F0 SLICE_329
ROUTE 14 2.994 R17C17D.F0 to R19C17D.LSR uart_data_120_N_1005_5 (to m_uart_tx/clk_en)
--------
17.067 (26.2% logic, 73.8% route), 10 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_347:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R18C14A.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Destination Clock Path sys_clk to SLICE_735:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.409 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 3.627 R12C11D.Q0 to R19C17D.CLK m_uart_tx/clk_en
--------
7.958 (19.4% logic, 80.6% route), 2 logic levels.
Error: The following path exceeds requirements by 11.431ns (weighted slack = -54.798ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i7 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i43 (to m_uart_tx/clk_en +)
FF m_uart_tx/uart_data_i42
Delay: 17.067ns (26.2% logic, 73.8% route), 10 logic levels.
Constraint Details:
17.067ns physical path delay SLICE_347 to SLICE_736 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
1.848ns delay constraint less
-4.036ns skew and
0.248ns LSR_SET requirement (totaling 5.636ns) by 11.431ns
Physical Path Details:
Data path SLICE_347 to SLICE_736:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C14A.CLK to R18C14A.Q1 SLICE_347 (from sys_clk_c)
ROUTE 17 1.524 R18C14A.Q1 to R16C14B.C1 temp_raw_data_7
CTOF_DEL --- 0.452 R16C14B.C1 to R16C14B.F1 m_bcd_8421/SLICE_829
ROUTE 6 1.357 R16C14B.F1 to R16C15A.D1 m_bcd_8421/n27684
CTOF_DEL --- 0.452 R16C15A.D1 to R16C15A.F1 m_bcd_8421/SLICE_833
ROUTE 1 0.882 R16C15A.F1 to R16C14A.B1 m_bcd_8421/n17629
CTOF_DEL --- 0.452 R16C14A.B1 to R16C14A.F1 m_bcd_8421/SLICE_837
ROUTE 2 1.163 R16C14A.F1 to R16C17C.A1 m_bcd_8421/n25255
CTOF_DEL --- 0.452 R16C17C.A1 to R16C17C.F1 m_bcd_8421/SLICE_830
ROUTE 1 0.854 R16C17C.F1 to R16C17A.A1 m_bcd_8421/n6_adj_1656
CTOF_DEL --- 0.452 R16C17A.A1 to R16C17A.F1 SLICE_334
ROUTE 4 0.925 R16C17A.F1 to R17C17B.B1 n25294
CTOF_DEL --- 0.452 R17C17B.B1 to R17C17B.F1 SLICE_319
ROUTE 4 1.619 R17C17B.F1 to R16C17B.D0 n27541
CTOF_DEL --- 0.452 R16C17B.D0 to R16C17B.F0 SLICE_616
ROUTE 1 0.384 R16C17B.F0 to R16C17B.C1 m_uart_tx/n4
CTOF_DEL --- 0.452 R16C17B.C1 to R16C17B.F1 SLICE_616
ROUTE 3 0.888 R16C17B.F1 to R17C17D.A0 n26544
CTOF_DEL --- 0.452 R17C17D.A0 to R17C17D.F0 SLICE_329
ROUTE 14 2.994 R17C17D.F0 to R17C17A.LSR uart_data_120_N_1005_5 (to m_uart_tx/clk_en)
--------
17.067 (26.2% logic, 73.8% route), 10 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_347:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R18C14A.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Destination Clock Path sys_clk to SLICE_736:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.409 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 3.627 R12C11D.Q0 to R17C17A.CLK m_uart_tx/clk_en
--------
7.958 (19.4% logic, 80.6% route), 2 logic levels.
Warning: 15.709MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ;
208 items scored, 130 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 7.063ns (weighted slack = -36.568ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/uart_data_i8 (from m_uart_tx/clk_en +)
Destination: FF Data in m_uart_tx/uart_out_48 (to m_uart_tx/clk_uart +)
Delay: 6.817ns (38.7% logic, 61.3% route), 5 logic levels.
Constraint Details:
6.817ns physical path delay SLICE_321 to m_uart_tx/SLICE_367 exceeds
(delay constraint based on source clock period of 8.859ns and destination clock period of 4.903ns)
0.947ns delay constraint less
1.043ns skew and
0.150ns DIN_SET requirement (totaling -0.246ns) by 7.063ns
Physical Path Details:
Data path SLICE_321 to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C17A.CLK to R18C17A.Q0 SLICE_321 (from m_uart_tx/clk_en)
ROUTE 1 1.734 R18C17A.Q0 to R17C21B.B1 m_uart_tx/uart_data_15
CTOOFX_DEL --- 0.661 R17C21B.B1 to R17C21B.OFX0 m_uart_tx/i24639/SLICE_386
ROUTE 1 0.885 R17C21B.OFX0 to R17C21D.B1 m_uart_tx/n28064
CTOF_DEL --- 0.452 R17C21D.B1 to R17C21D.F1 SLICE_740
ROUTE 1 0.678 R17C21D.F1 to R15C21D.C0 m_uart_tx/n28065
CTOF_DEL --- 0.452 R15C21D.C0 to R15C21D.F0 m_uart_tx/SLICE_976
ROUTE 1 0.885 R15C21D.F0 to R15C21A.B0 m_uart_tx/n28073
CTOOFX_DEL --- 0.661 R15C21A.B0 to R15C21A.OFX0 m_uart_tx/SLICE_367
ROUTE 1 0.000 R15C21A.OFX0 to R15C21A.DI0 m_uart_tx/uart_out_N_1245 (to m_uart_tx/clk_uart)
--------
6.817 (38.7% logic, 61.3% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_321:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.409 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 3.627 R12C11D.Q0 to R18C17A.CLK m_uart_tx/clk_en
--------
7.958 (19.4% logic, 80.6% route), 2 logic levels.
Destination Clock Path sys_clk to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R13C31A.CLK sys_clk_c
REG_DEL --- 0.409 R13C31A.CLK to R13C31A.Q0 m_uart_tx/SLICE_311
ROUTE 8 2.584 R13C31A.Q0 to R15C21A.CLK m_uart_tx/clk_uart
--------
6.915 (22.3% logic, 77.7% route), 2 logic levels.
Error: The following path exceeds requirements by 6.653ns (weighted slack = -34.445ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/uart_data_i7 (from m_uart_tx/clk_en +)
Destination: FF Data in m_uart_tx/uart_out_48 (to m_uart_tx/clk_uart +)
Delay: 6.407ns (41.1% logic, 58.9% route), 5 logic levels.
Constraint Details:
6.407ns physical path delay SLICE_320 to m_uart_tx/SLICE_367 exceeds
(delay constraint based on source clock period of 8.859ns and destination clock period of 4.903ns)
0.947ns delay constraint less
1.043ns skew and
0.150ns DIN_SET requirement (totaling -0.246ns) by 6.653ns
Physical Path Details:
Data path SLICE_320 to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R16C15C.CLK to R16C15C.Q1 SLICE_320 (from m_uart_tx/clk_en)
ROUTE 1 1.324 R16C15C.Q1 to R17C21B.A1 m_uart_tx/uart_data_14
CTOOFX_DEL --- 0.661 R17C21B.A1 to R17C21B.OFX0 m_uart_tx/i24639/SLICE_386
ROUTE 1 0.885 R17C21B.OFX0 to R17C21D.B1 m_uart_tx/n28064
CTOF_DEL --- 0.452 R17C21D.B1 to R17C21D.F1 SLICE_740
ROUTE 1 0.678 R17C21D.F1 to R15C21D.C0 m_uart_tx/n28065
CTOF_DEL --- 0.452 R15C21D.C0 to R15C21D.F0 m_uart_tx/SLICE_976
ROUTE 1 0.885 R15C21D.F0 to R15C21A.B0 m_uart_tx/n28073
CTOOFX_DEL --- 0.661 R15C21A.B0 to R15C21A.OFX0 m_uart_tx/SLICE_367
ROUTE 1 0.000 R15C21A.OFX0 to R15C21A.DI0 m_uart_tx/uart_out_N_1245 (to m_uart_tx/clk_uart)
--------
6.407 (41.1% logic, 58.9% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_320:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.409 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 3.627 R12C11D.Q0 to R16C15C.CLK m_uart_tx/clk_en
--------
7.958 (19.4% logic, 80.6% route), 2 logic levels.
Destination Clock Path sys_clk to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R13C31A.CLK sys_clk_c
REG_DEL --- 0.409 R13C31A.CLK to R13C31A.Q0 m_uart_tx/SLICE_311
ROUTE 8 2.584 R13C31A.Q0 to R15C21A.CLK m_uart_tx/clk_uart
--------
6.915 (22.3% logic, 77.7% route), 2 logic levels.
Error: The following path exceeds requirements by 6.612ns (weighted slack = -34.233ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/uart_data_i1 (from m_uart_tx/clk_en +)
Destination: FF Data in m_uart_tx/uart_out_48 (to m_uart_tx/clk_uart +)
Delay: 6.366ns (41.4% logic, 58.6% route), 5 logic levels.
Constraint Details:
6.366ns physical path delay SLICE_319 to m_uart_tx/SLICE_367 exceeds
(delay constraint based on source clock period of 8.859ns and destination clock period of 4.903ns)
0.947ns delay constraint less
1.043ns skew and
0.150ns DIN_SET requirement (totaling -0.246ns) by 6.612ns
Physical Path Details:
Data path SLICE_319 to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R17C17B.CLK to R17C17B.Q0 SLICE_319 (from m_uart_tx/clk_en)
ROUTE 1 1.283 R17C17B.Q0 to R17C21B.B0 m_uart_tx/uart_data_3
CTOOFX_DEL --- 0.661 R17C21B.B0 to R17C21B.OFX0 m_uart_tx/i24639/SLICE_386
ROUTE 1 0.885 R17C21B.OFX0 to R17C21D.B1 m_uart_tx/n28064
CTOF_DEL --- 0.452 R17C21D.B1 to R17C21D.F1 SLICE_740
ROUTE 1 0.678 R17C21D.F1 to R15C21D.C0 m_uart_tx/n28065
CTOF_DEL --- 0.452 R15C21D.C0 to R15C21D.F0 m_uart_tx/SLICE_976
ROUTE 1 0.885 R15C21D.F0 to R15C21A.B0 m_uart_tx/n28073
CTOOFX_DEL --- 0.661 R15C21A.B0 to R15C21A.OFX0 m_uart_tx/SLICE_367
ROUTE 1 0.000 R15C21A.OFX0 to R15C21A.DI0 m_uart_tx/uart_out_N_1245 (to m_uart_tx/clk_uart)
--------
6.366 (41.4% logic, 58.6% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_319:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.409 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 3.627 R12C11D.Q0 to R17C17B.CLK m_uart_tx/clk_en
--------
7.958 (19.4% logic, 80.6% route), 2 logic levels.
Destination Clock Path sys_clk to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R13C31A.CLK sys_clk_c
REG_DEL --- 0.409 R13C31A.CLK to R13C31A.Q0 m_uart_tx/SLICE_311
ROUTE 8 2.584 R13C31A.Q0 to R15C21A.CLK m_uart_tx/clk_uart
--------
6.915 (22.3% logic, 77.7% route), 2 logic levels.
Error: The following path exceeds requirements by 6.532ns (weighted slack = -33.819ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/uart_data_i49 (from m_uart_tx/clk_en +)
Destination: FF Data in m_uart_tx/uart_out_48 (to m_uart_tx/clk_uart +)
Delay: 6.286ns (41.9% logic, 58.1% route), 5 logic levels.
Constraint Details:
6.286ns physical path delay SLICE_334 to m_uart_tx/SLICE_367 exceeds
(delay constraint based on source clock period of 8.859ns and destination clock period of 4.903ns)
0.947ns delay constraint less
1.043ns skew and
0.150ns DIN_SET requirement (totaling -0.246ns) by 6.532ns
Physical Path Details:
Data path SLICE_334 to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R16C17A.CLK to R16C17A.Q0 SLICE_334 (from m_uart_tx/clk_en)
ROUTE 6 1.612 R16C17A.Q0 to R16C19D.B1 m_uart_tx/uart_data_107
CTOF_DEL --- 0.452 R16C19D.B1 to R16C19D.F1 SLICE_942
ROUTE 1 0.659 R16C19D.F1 to R16C19B.C0 m_uart_tx/n27234
CTOOFX_DEL --- 0.661 R16C19B.C0 to R16C19B.OFX0 m_uart_tx/i24309/SLICE_376
ROUTE 1 0.541 R16C19B.OFX0 to R16C20B.D0 m_uart_tx/n27239
CTOF_DEL --- 0.452 R16C20B.D0 to R16C20B.F0 SLICE_743
ROUTE 1 0.839 R16C20B.F0 to R15C21A.D1 m_uart_tx/n25743
CTOOFX_DEL --- 0.661 R15C21A.D1 to R15C21A.OFX0 m_uart_tx/SLICE_367
ROUTE 1 0.000 R15C21A.OFX0 to R15C21A.DI0 m_uart_tx/uart_out_N_1245 (to m_uart_tx/clk_uart)
--------
6.286 (41.9% logic, 58.1% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_334:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.409 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 3.627 R12C11D.Q0 to R16C17A.CLK m_uart_tx/clk_en
--------
7.958 (19.4% logic, 80.6% route), 2 logic levels.
Destination Clock Path sys_clk to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R13C31A.CLK sys_clk_c
REG_DEL --- 0.409 R13C31A.CLK to R13C31A.Q0 m_uart_tx/SLICE_311
ROUTE 8 2.584 R13C31A.Q0 to R15C21A.CLK m_uart_tx/clk_uart
--------
6.915 (22.3% logic, 77.7% route), 2 logic levels.
Error: The following path exceeds requirements by 6.458ns (weighted slack = -33.436ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/uart_data_i43 (from m_uart_tx/clk_en +)
Destination: FF Data in m_uart_tx/uart_out_48 (to m_uart_tx/clk_uart +)
Delay: 6.212ns (45.8% logic, 54.2% route), 5 logic levels.
Constraint Details:
6.212ns physical path delay SLICE_736 to m_uart_tx/SLICE_367 exceeds
(delay constraint based on source clock period of 8.859ns and destination clock period of 4.903ns)
0.947ns delay constraint less
1.043ns skew and
0.150ns DIN_SET requirement (totaling -0.246ns) by 6.458ns
Physical Path Details:
Data path SLICE_736 to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R17C17A.CLK to R17C17A.Q1 SLICE_736 (from m_uart_tx/clk_en)
ROUTE 1 1.149 R17C17A.Q1 to R17C20C.A0 m_uart_tx/uart_data_96
CTOOFX_DEL --- 0.661 R17C20C.A0 to R17C20C.OFX0 m_uart_tx/i24307/SLICE_377
ROUTE 1 0.839 R17C20C.OFX0 to R16C19B.D0 m_uart_tx/n27237
CTOOFX_DEL --- 0.661 R16C19B.D0 to R16C19B.OFX0 m_uart_tx/i24309/SLICE_376
ROUTE 1 0.541 R16C19B.OFX0 to R16C20B.D0 m_uart_tx/n27239
CTOF_DEL --- 0.452 R16C20B.D0 to R16C20B.F0 SLICE_743
ROUTE 1 0.839 R16C20B.F0 to R15C21A.D1 m_uart_tx/n25743
CTOOFX_DEL --- 0.661 R15C21A.D1 to R15C21A.OFX0 m_uart_tx/SLICE_367
ROUTE 1 0.000 R15C21A.OFX0 to R15C21A.DI0 m_uart_tx/uart_out_N_1245 (to m_uart_tx/clk_uart)
--------
6.212 (45.8% logic, 54.2% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_736:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.409 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 3.627 R12C11D.Q0 to R17C17A.CLK m_uart_tx/clk_en
--------
7.958 (19.4% logic, 80.6% route), 2 logic levels.
Destination Clock Path sys_clk to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R13C31A.CLK sys_clk_c
REG_DEL --- 0.409 R13C31A.CLK to R13C31A.Q0 m_uart_tx/SLICE_311
ROUTE 8 2.584 R13C31A.Q0 to R15C21A.CLK m_uart_tx/clk_uart
--------
6.915 (22.3% logic, 77.7% route), 2 logic levels.
Error: The following path exceeds requirements by 6.439ns (weighted slack = -33.337ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/uart_data_i37 (from m_uart_tx/clk_en +)
Destination: FF Data in m_uart_tx/uart_out_48 (to m_uart_tx/clk_uart +)
Delay: 6.193ns (38.9% logic, 61.1% route), 5 logic levels.
Constraint Details:
6.193ns physical path delay SLICE_329 to m_uart_tx/SLICE_367 exceeds
(delay constraint based on source clock period of 8.859ns and destination clock period of 4.903ns)
0.947ns delay constraint less
1.043ns skew and
0.150ns DIN_SET requirement (totaling -0.246ns) by 6.439ns
Physical Path Details:
Data path SLICE_329 to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R17C17D.CLK to R17C17D.Q0 SLICE_329 (from m_uart_tx/clk_en)
ROUTE 10 1.547 R17C17D.Q0 to R15C17B.D0 m_uart_tx/uart_data_85
CTOOFX_DEL --- 0.661 R15C17B.D0 to R15C17B.OFX0 m_uart_tx/i24645/SLICE_384
ROUTE 1 0.000 R15C17B.OFX0 to R15C17A.FXA m_uart_tx/n28071
FXTOOFX_DE --- 0.223 R15C17A.FXA to R15C17A.OFX1 m_uart_tx/i24642/SLICE_385
ROUTE 1 1.355 R15C17A.OFX1 to R15C21D.B0 m_uart_tx/n28072
CTOF_DEL --- 0.452 R15C21D.B0 to R15C21D.F0 m_uart_tx/SLICE_976
ROUTE 1 0.885 R15C21D.F0 to R15C21A.B0 m_uart_tx/n28073
CTOOFX_DEL --- 0.661 R15C21A.B0 to R15C21A.OFX0 m_uart_tx/SLICE_367
ROUTE 1 0.000 R15C21A.OFX0 to R15C21A.DI0 m_uart_tx/uart_out_N_1245 (to m_uart_tx/clk_uart)
--------
6.193 (38.9% logic, 61.1% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_329:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.409 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 3.627 R12C11D.Q0 to R17C17D.CLK m_uart_tx/clk_en
--------
7.958 (19.4% logic, 80.6% route), 2 logic levels.
Destination Clock Path sys_clk to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R13C31A.CLK sys_clk_c
REG_DEL --- 0.409 R13C31A.CLK to R13C31A.Q0 m_uart_tx/SLICE_311
ROUTE 8 2.584 R13C31A.Q0 to R15C21A.CLK m_uart_tx/clk_uart
--------
6.915 (22.3% logic, 77.7% route), 2 logic levels.
Error: The following path exceeds requirements by 6.300ns (weighted slack = -32.618ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/uart_data_i49 (from m_uart_tx/clk_en +)
Destination: FF Data in m_uart_tx/uart_out_48 (to m_uart_tx/clk_uart +)
Delay: 6.054ns (43.2% logic, 56.8% route), 5 logic levels.
Constraint Details:
6.054ns physical path delay SLICE_334 to m_uart_tx/SLICE_367 exceeds
(delay constraint based on source clock period of 8.859ns and destination clock period of 4.903ns)
0.947ns delay constraint less
1.043ns skew and
0.150ns DIN_SET requirement (totaling -0.246ns) by 6.300ns
Physical Path Details:
Data path SLICE_334 to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R16C17A.CLK to R16C17A.Q0 SLICE_334 (from m_uart_tx/clk_en)
ROUTE 6 1.612 R16C17A.Q0 to R16C18D.B1 m_uart_tx/uart_data_107
CTOOFX_DEL --- 0.661 R16C18D.B1 to R16C18D.OFX0 m_uart_tx/i23341/SLICE_387
ROUTE 1 0.954 R16C18D.OFX0 to R15C19D.C0 m_uart_tx/n25696
CTOOFX_DEL --- 0.661 R15C19D.C0 to R15C19D.OFX0 m_uart_tx/i23384/SLICE_379
ROUTE 1 0.000 R15C19D.OFX0 to R15C19C.FXA m_uart_tx/n25739
FXTOOFX_DE --- 0.223 R15C19C.FXA to R15C19C.OFX1 m_uart_tx/i23381/SLICE_383
ROUTE 1 0.873 R15C19C.OFX1 to R15C21A.A1 m_uart_tx/n25742
CTOOFX_DEL --- 0.661 R15C21A.A1 to R15C21A.OFX0 m_uart_tx/SLICE_367
ROUTE 1 0.000 R15C21A.OFX0 to R15C21A.DI0 m_uart_tx/uart_out_N_1245 (to m_uart_tx/clk_uart)
--------
6.054 (43.2% logic, 56.8% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_334:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.409 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 3.627 R12C11D.Q0 to R16C17A.CLK m_uart_tx/clk_en
--------
7.958 (19.4% logic, 80.6% route), 2 logic levels.
Destination Clock Path sys_clk to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R13C31A.CLK sys_clk_c
REG_DEL --- 0.409 R13C31A.CLK to R13C31A.Q0 m_uart_tx/SLICE_311
ROUTE 8 2.584 R13C31A.Q0 to R15C21A.CLK m_uart_tx/clk_uart
--------
6.915 (22.3% logic, 77.7% route), 2 logic levels.
Error: The following path exceeds requirements by 6.251ns (weighted slack = -32.364ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/uart_data_i37 (from m_uart_tx/clk_en +)
Destination: FF Data in m_uart_tx/uart_out_48 (to m_uart_tx/clk_uart +)
Delay: 6.005ns (40.1% logic, 59.9% route), 5 logic levels.
Constraint Details:
6.005ns physical path delay SLICE_329 to m_uart_tx/SLICE_367 exceeds
(delay constraint based on source clock period of 8.859ns and destination clock period of 4.903ns)
0.947ns delay constraint less
1.043ns skew and
0.150ns DIN_SET requirement (totaling -0.246ns) by 6.251ns
Physical Path Details:
Data path SLICE_329 to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R17C17D.CLK to R17C17D.Q0 SLICE_329 (from m_uart_tx/clk_en)
ROUTE 10 1.359 R17C17D.Q0 to R15C17A.D1 m_uart_tx/uart_data_85
CTOOFX_DEL --- 0.661 R15C17A.D1 to R15C17A.OFX0 m_uart_tx/i24642/SLICE_385
ROUTE 1 0.000 R15C17A.OFX0 to R15C17A.FXB m_uart_tx/n28068
FXTOOFX_DE --- 0.223 R15C17A.FXB to R15C17A.OFX1 m_uart_tx/i24642/SLICE_385
ROUTE 1 1.355 R15C17A.OFX1 to R15C21D.B0 m_uart_tx/n28072
CTOF_DEL --- 0.452 R15C21D.B0 to R15C21D.F0 m_uart_tx/SLICE_976
ROUTE 1 0.885 R15C21D.F0 to R15C21A.B0 m_uart_tx/n28073
CTOOFX_DEL --- 0.661 R15C21A.B0 to R15C21A.OFX0 m_uart_tx/SLICE_367
ROUTE 1 0.000 R15C21A.OFX0 to R15C21A.DI0 m_uart_tx/uart_out_N_1245 (to m_uart_tx/clk_uart)
--------
6.005 (40.1% logic, 59.9% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_329:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.409 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 3.627 R12C11D.Q0 to R17C17D.CLK m_uart_tx/clk_en
--------
7.958 (19.4% logic, 80.6% route), 2 logic levels.
Destination Clock Path sys_clk to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R13C31A.CLK sys_clk_c
REG_DEL --- 0.409 R13C31A.CLK to R13C31A.Q0 m_uart_tx/SLICE_311
ROUTE 8 2.584 R13C31A.Q0 to R15C21A.CLK m_uart_tx/clk_uart
--------
6.915 (22.3% logic, 77.7% route), 2 logic levels.
Error: The following path exceeds requirements by 6.218ns (weighted slack = -32.193ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/uart_data_i42 (from m_uart_tx/clk_en +)
Destination: FF Data in m_uart_tx/uart_out_48 (to m_uart_tx/clk_uart +)
Delay: 5.972ns (43.8% logic, 56.2% route), 5 logic levels.
Constraint Details:
5.972ns physical path delay SLICE_736 to m_uart_tx/SLICE_367 exceeds
(delay constraint based on source clock period of 8.859ns and destination clock period of 4.903ns)
0.947ns delay constraint less
1.043ns skew and
0.150ns DIN_SET requirement (totaling -0.246ns) by 6.218ns
Physical Path Details:
Data path SLICE_736 to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R17C17A.CLK to R17C17A.Q0 SLICE_736 (from m_uart_tx/clk_en)
ROUTE 1 1.129 R17C17A.Q0 to R18C17B.C1 m_uart_tx/uart_data_95
CTOOFX_DEL --- 0.661 R18C17B.C1 to R18C17B.OFX0 m_uart_tx/i_6__I_0_57_i91/SLICE_382
ROUTE 1 1.355 R18C17B.OFX0 to R15C19C.B1 m_uart_tx/n91
CTOOFX_DEL --- 0.661 R15C19C.B1 to R15C19C.OFX0 m_uart_tx/i23381/SLICE_383
ROUTE 1 0.000 R15C19C.OFX0 to R15C19C.FXB m_uart_tx/n25736
FXTOOFX_DE --- 0.223 R15C19C.FXB to R15C19C.OFX1 m_uart_tx/i23381/SLICE_383
ROUTE 1 0.873 R15C19C.OFX1 to R15C21A.A1 m_uart_tx/n25742
CTOOFX_DEL --- 0.661 R15C21A.A1 to R15C21A.OFX0 m_uart_tx/SLICE_367
ROUTE 1 0.000 R15C21A.OFX0 to R15C21A.DI0 m_uart_tx/uart_out_N_1245 (to m_uart_tx/clk_uart)
--------
5.972 (43.8% logic, 56.2% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_736:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.409 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 3.627 R12C11D.Q0 to R17C17A.CLK m_uart_tx/clk_en
--------
7.958 (19.4% logic, 80.6% route), 2 logic levels.
Destination Clock Path sys_clk to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R13C31A.CLK sys_clk_c
REG_DEL --- 0.409 R13C31A.CLK to R13C31A.Q0 m_uart_tx/SLICE_311
ROUTE 8 2.584 R13C31A.Q0 to R15C21A.CLK m_uart_tx/clk_uart
--------
6.915 (22.3% logic, 77.7% route), 2 logic levels.
Error: The following path exceeds requirements by 6.194ns (weighted slack = -32.069ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/uart_data_i46 (from m_uart_tx/clk_en +)
Destination: FF Data in m_uart_tx/uart_out_48 (to m_uart_tx/clk_uart +)
Delay: 5.948ns (47.8% logic, 52.2% route), 5 logic levels.
Constraint Details:
5.948ns physical path delay SLICE_734 to m_uart_tx/SLICE_367 exceeds
(delay constraint based on source clock period of 8.859ns and destination clock period of 4.903ns)
0.947ns delay constraint less
1.043ns skew and
0.150ns DIN_SET requirement (totaling -0.246ns) by 6.194ns
Physical Path Details:
Data path SLICE_734 to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R17C20A.CLK to R17C20A.Q1 SLICE_734 (from m_uart_tx/clk_en)
ROUTE 1 0.885 R17C20A.Q1 to R17C20C.B1 m_uart_tx/uart_data_104
CTOOFX_DEL --- 0.661 R17C20C.B1 to R17C20C.OFX0 m_uart_tx/i24307/SLICE_377
ROUTE 1 0.839 R17C20C.OFX0 to R16C19B.D0 m_uart_tx/n27237
CTOOFX_DEL --- 0.661 R16C19B.D0 to R16C19B.OFX0 m_uart_tx/i24309/SLICE_376
ROUTE 1 0.541 R16C19B.OFX0 to R16C20B.D0 m_uart_tx/n27239
CTOF_DEL --- 0.452 R16C20B.D0 to R16C20B.F0 SLICE_743
ROUTE 1 0.839 R16C20B.F0 to R15C21A.D1 m_uart_tx/n25743
CTOOFX_DEL --- 0.661 R15C21A.D1 to R15C21A.OFX0 m_uart_tx/SLICE_367
ROUTE 1 0.000 R15C21A.OFX0 to R15C21A.DI0 m_uart_tx/uart_out_N_1245 (to m_uart_tx/clk_uart)
--------
5.948 (47.8% logic, 52.2% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_734:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.409 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 3.627 R12C11D.Q0 to R17C20A.CLK m_uart_tx/clk_en
--------
7.958 (19.4% logic, 80.6% route), 2 logic levels.
Destination Clock Path sys_clk to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R13C31A.CLK sys_clk_c
REG_DEL --- 0.409 R13C31A.CLK to R13C31A.Q0 m_uart_tx/SLICE_311
ROUTE 8 2.584 R13C31A.Q0 to R15C21A.CLK m_uart_tx/clk_uart
--------
6.915 (22.3% logic, 77.7% route), 2 logic levels.
Warning: 24.116MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ;
1337 items scored, 1027 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 12.718ns (weighted slack = -185.216ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/min_set_high__i3 (from m_clock/clk_500ms +)
Destination: FF Data in m_clock/time_min_low_i2 (to m_clock/clk_1ms +)
Delay: 8.184ns (29.6% logic, 70.4% route), 5 logic levels.
Constraint Details:
8.184ns physical path delay m_clock/SLICE_289 to m_clock/SLICE_357 exceeds
(delay constraint based on source clock period of 7.300ns and destination clock period of 4.602ns)
0.316ns delay constraint less
4.700ns skew and
0.150ns DIN_SET requirement (totaling -4.534ns) by 12.718ns
Physical Path Details:
Data path m_clock/SLICE_289 to m_clock/SLICE_357:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C21A.CLK to R18C21A.Q0 m_clock/SLICE_289 (from m_clock/clk_500ms)
ROUTE 4 1.906 R18C21A.Q0 to R20C21A.A0 m_clock/min_set_high_3
CTOF_DEL --- 0.452 R20C21A.A0 to R20C21A.F0 m_clock/SLICE_963
ROUTE 1 0.885 R20C21A.F0 to R20C21D.B0 m_clock/n28
CTOF_DEL --- 0.452 R20C21D.B0 to R20C21D.F0 m_clock/SLICE_812
ROUTE 4 0.866 R20C21D.F0 to R20C20B.A0 m_clock/n25895
CTOF_DEL --- 0.452 R20C20B.A0 to R20C20B.F0 m_clock/SLICE_998
ROUTE 28 2.101 R20C20B.F0 to R20C22C.B0 m_clock/clk_1ms_enable_32
CTOOFX_DEL --- 0.661 R20C22C.B0 to R20C22C.OFX0 m_clock/SLICE_357
ROUTE 1 0.000 R20C22C.OFX0 to R20C22C.DI0 m_clock/time_min_low_3_N_1477_2 (to m_clock/clk_1ms)
--------
8.184 (29.6% logic, 70.4% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_289:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.409 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 4.291 R4C16D.Q0 to R18C21A.CLK m_clock/clk_500ms
--------
11.691 (16.7% logic, 83.3% route), 3 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_357:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C22C.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Error: The following path exceeds requirements by 12.718ns (weighted slack = -185.216ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/min_set_high__i3 (from m_clock/clk_500ms +)
Destination: FF Data in m_clock/time_min_low_i2 (to m_clock/clk_1ms +)
Delay: 8.184ns (29.6% logic, 70.4% route), 5 logic levels.
Constraint Details:
8.184ns physical path delay m_clock/SLICE_289 to m_clock/SLICE_357 exceeds
(delay constraint based on source clock period of 7.300ns and destination clock period of 4.602ns)
0.316ns delay constraint less
4.700ns skew and
0.150ns DIN_SET requirement (totaling -4.534ns) by 12.718ns
Physical Path Details:
Data path m_clock/SLICE_289 to m_clock/SLICE_357:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C21A.CLK to R18C21A.Q0 m_clock/SLICE_289 (from m_clock/clk_500ms)
ROUTE 4 1.906 R18C21A.Q0 to R20C21A.A0 m_clock/min_set_high_3
CTOF_DEL --- 0.452 R20C21A.A0 to R20C21A.F0 m_clock/SLICE_963
ROUTE 1 0.885 R20C21A.F0 to R20C21D.B0 m_clock/n28
CTOF_DEL --- 0.452 R20C21D.B0 to R20C21D.F0 m_clock/SLICE_812
ROUTE 4 0.866 R20C21D.F0 to R20C20B.A0 m_clock/n25895
CTOF_DEL --- 0.452 R20C20B.A0 to R20C20B.F0 m_clock/SLICE_998
ROUTE 28 2.101 R20C20B.F0 to R20C22C.B1 m_clock/clk_1ms_enable_32
CTOOFX_DEL --- 0.661 R20C22C.B1 to R20C22C.OFX0 m_clock/SLICE_357
ROUTE 1 0.000 R20C22C.OFX0 to R20C22C.DI0 m_clock/time_min_low_3_N_1477_2 (to m_clock/clk_1ms)
--------
8.184 (29.6% logic, 70.4% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_289:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.409 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 4.291 R4C16D.Q0 to R18C21A.CLK m_clock/clk_500ms
--------
11.691 (16.7% logic, 83.3% route), 3 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_357:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C22C.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Error: The following path exceeds requirements by 12.655ns (weighted slack = -184.298ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/min_set_high__i3 (from m_clock/clk_500ms +)
Destination: FF Data in m_clock/time_min_low_i3 (to m_clock/clk_1ms +)
Delay: 8.121ns (27.3% logic, 72.7% route), 5 logic levels.
Constraint Details:
8.121ns physical path delay m_clock/SLICE_289 to m_clock/SLICE_358 exceeds
(delay constraint based on source clock period of 7.300ns and destination clock period of 4.602ns)
0.316ns delay constraint less
4.700ns skew and
0.150ns DIN_SET requirement (totaling -4.534ns) by 12.655ns
Physical Path Details:
Data path m_clock/SLICE_289 to m_clock/SLICE_358:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C21A.CLK to R18C21A.Q0 m_clock/SLICE_289 (from m_clock/clk_500ms)
ROUTE 4 1.906 R18C21A.Q0 to R20C21A.A0 m_clock/min_set_high_3
CTOF_DEL --- 0.452 R20C21A.A0 to R20C21A.F0 m_clock/SLICE_963
ROUTE 1 0.885 R20C21A.F0 to R20C21D.B0 m_clock/n28
CTOF_DEL --- 0.452 R20C21D.B0 to R20C21D.F0 m_clock/SLICE_812
ROUTE 4 0.866 R20C21D.F0 to R20C20B.A0 m_clock/n25895
CTOF_DEL --- 0.452 R20C20B.A0 to R20C20B.F0 m_clock/SLICE_998
ROUTE 28 2.247 R20C20B.F0 to R20C23B.C0 m_clock/clk_1ms_enable_32
CTOF_DEL --- 0.452 R20C23B.C0 to R20C23B.F0 m_clock/SLICE_358
ROUTE 1 0.000 R20C23B.F0 to R20C23B.DI0 m_clock/time_min_low_3_N_1477_3 (to m_clock/clk_1ms)
--------
8.121 (27.3% logic, 72.7% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_289:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.409 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 4.291 R4C16D.Q0 to R18C21A.CLK m_clock/clk_500ms
--------
11.691 (16.7% logic, 83.3% route), 3 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_358:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C23B.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Error: The following path exceeds requirements by 12.024ns (weighted slack = -175.109ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/min_set_low_i0_i0 (from m_clock/clk_500ms +)
Destination: FF Data in m_clock/time_min_low_i2 (to m_clock/clk_1ms +)
Delay: 7.490ns (26.4% logic, 73.6% route), 4 logic levels.
Constraint Details:
7.490ns physical path delay m_clock/SLICE_290 to m_clock/SLICE_357 exceeds
(delay constraint based on source clock period of 7.300ns and destination clock period of 4.602ns)
0.316ns delay constraint less
4.700ns skew and
0.150ns DIN_SET requirement (totaling -4.534ns) by 12.024ns
Physical Path Details:
Data path m_clock/SLICE_290 to m_clock/SLICE_357:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C25A.CLK to R20C25A.Q0 m_clock/SLICE_290 (from m_clock/clk_500ms)
ROUTE 2 2.110 R20C25A.Q0 to R20C17B.B0 m_clock/min_set_low_0
CTOF_DEL --- 0.452 R20C17B.B0 to R20C17B.F0 m_clock/SLICE_808
ROUTE 4 1.305 R20C17B.F0 to R20C20B.B0 m_clock/n25
CTOF_DEL --- 0.452 R20C20B.B0 to R20C20B.F0 m_clock/SLICE_998
ROUTE 28 2.101 R20C20B.F0 to R20C22C.B1 m_clock/clk_1ms_enable_32
CTOOFX_DEL --- 0.661 R20C22C.B1 to R20C22C.OFX0 m_clock/SLICE_357
ROUTE 1 0.000 R20C22C.OFX0 to R20C22C.DI0 m_clock/time_min_low_3_N_1477_2 (to m_clock/clk_1ms)
--------
7.490 (26.4% logic, 73.6% route), 4 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_290:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.409 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 4.291 R4C16D.Q0 to R20C25A.CLK m_clock/clk_500ms
--------
11.691 (16.7% logic, 83.3% route), 3 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_357:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C22C.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Error: The following path exceeds requirements by 12.024ns (weighted slack = -175.109ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/min_set_low_i0_i0 (from m_clock/clk_500ms +)
Destination: FF Data in m_clock/time_min_low_i2 (to m_clock/clk_1ms +)
Delay: 7.490ns (26.4% logic, 73.6% route), 4 logic levels.
Constraint Details:
7.490ns physical path delay m_clock/SLICE_290 to m_clock/SLICE_357 exceeds
(delay constraint based on source clock period of 7.300ns and destination clock period of 4.602ns)
0.316ns delay constraint less
4.700ns skew and
0.150ns DIN_SET requirement (totaling -4.534ns) by 12.024ns
Physical Path Details:
Data path m_clock/SLICE_290 to m_clock/SLICE_357:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C25A.CLK to R20C25A.Q0 m_clock/SLICE_290 (from m_clock/clk_500ms)
ROUTE 2 2.110 R20C25A.Q0 to R20C17B.B0 m_clock/min_set_low_0
CTOF_DEL --- 0.452 R20C17B.B0 to R20C17B.F0 m_clock/SLICE_808
ROUTE 4 1.305 R20C17B.F0 to R20C20B.B0 m_clock/n25
CTOF_DEL --- 0.452 R20C20B.B0 to R20C20B.F0 m_clock/SLICE_998
ROUTE 28 2.101 R20C20B.F0 to R20C22C.B0 m_clock/clk_1ms_enable_32
CTOOFX_DEL --- 0.661 R20C22C.B0 to R20C22C.OFX0 m_clock/SLICE_357
ROUTE 1 0.000 R20C22C.OFX0 to R20C22C.DI0 m_clock/time_min_low_3_N_1477_2 (to m_clock/clk_1ms)
--------
7.490 (26.4% logic, 73.6% route), 4 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_290:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.409 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 4.291 R4C16D.Q0 to R20C25A.CLK m_clock/clk_500ms
--------
11.691 (16.7% logic, 83.3% route), 3 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_357:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C22C.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Error: The following path exceeds requirements by 11.961ns (weighted slack = -174.192ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/min_set_low_i0_i0 (from m_clock/clk_500ms +)
Destination: FF Data in m_clock/time_min_low_i3 (to m_clock/clk_1ms +)
Delay: 7.427ns (23.8% logic, 76.2% route), 4 logic levels.
Constraint Details:
7.427ns physical path delay m_clock/SLICE_290 to m_clock/SLICE_358 exceeds
(delay constraint based on source clock period of 7.300ns and destination clock period of 4.602ns)
0.316ns delay constraint less
4.700ns skew and
0.150ns DIN_SET requirement (totaling -4.534ns) by 11.961ns
Physical Path Details:
Data path m_clock/SLICE_290 to m_clock/SLICE_358:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C25A.CLK to R20C25A.Q0 m_clock/SLICE_290 (from m_clock/clk_500ms)
ROUTE 2 2.110 R20C25A.Q0 to R20C17B.B0 m_clock/min_set_low_0
CTOF_DEL --- 0.452 R20C17B.B0 to R20C17B.F0 m_clock/SLICE_808
ROUTE 4 1.305 R20C17B.F0 to R20C20B.B0 m_clock/n25
CTOF_DEL --- 0.452 R20C20B.B0 to R20C20B.F0 m_clock/SLICE_998
ROUTE 28 2.247 R20C20B.F0 to R20C23B.C0 m_clock/clk_1ms_enable_32
CTOF_DEL --- 0.452 R20C23B.C0 to R20C23B.F0 m_clock/SLICE_358
ROUTE 1 0.000 R20C23B.F0 to R20C23B.DI0 m_clock/time_min_low_3_N_1477_3 (to m_clock/clk_1ms)
--------
7.427 (23.8% logic, 76.2% route), 4 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_290:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.409 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 4.291 R4C16D.Q0 to R20C25A.CLK m_clock/clk_500ms
--------
11.691 (16.7% logic, 83.3% route), 3 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_358:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C23B.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Error: The following path exceeds requirements by 11.832ns (weighted slack = -172.313ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/min_set_high__i3 (from m_clock/clk_500ms +)
Destination: FF Data in m_clock/time_min_high_i3 (to m_clock/clk_1ms +)
FF m_clock/time_min_high_i2
Delay: 7.199ns (30.8% logic, 69.2% route), 5 logic levels.
Constraint Details:
7.199ns physical path delay m_clock/SLICE_289 to m_clock/SLICE_355 exceeds
(delay constraint based on source clock period of 7.300ns and destination clock period of 4.602ns)
0.316ns delay constraint less
4.700ns skew and
0.249ns CE_SET requirement (totaling -4.633ns) by 11.832ns
Physical Path Details:
Data path m_clock/SLICE_289 to m_clock/SLICE_355:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C21A.CLK to R18C21A.Q0 m_clock/SLICE_289 (from m_clock/clk_500ms)
ROUTE 4 1.906 R18C21A.Q0 to R20C21A.A0 m_clock/min_set_high_3
CTOF_DEL --- 0.452 R20C21A.A0 to R20C21A.F0 m_clock/SLICE_963
ROUTE 1 0.885 R20C21A.F0 to R20C21D.B0 m_clock/n28
CTOF_DEL --- 0.452 R20C21D.B0 to R20C21D.F0 m_clock/SLICE_812
ROUTE 4 0.866 R20C21D.F0 to R20C20B.A0 m_clock/n25895
CTOF_DEL --- 0.452 R20C20B.A0 to R20C20B.F0 m_clock/SLICE_998
ROUTE 28 0.741 R20C20B.F0 to R19C20B.C1 m_clock/clk_1ms_enable_32
CTOF_DEL --- 0.452 R19C20B.C1 to R19C20B.F1 m_clock/SLICE_815
ROUTE 2 0.584 R19C20B.F1 to R19C20A.CE m_clock/clk_1ms_enable_27 (to m_clock/clk_1ms)
--------
7.199 (30.8% logic, 69.2% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_289:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.409 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 4.291 R4C16D.Q0 to R18C21A.CLK m_clock/clk_500ms
--------
11.691 (16.7% logic, 83.3% route), 3 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_355:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R19C20A.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Error: The following path exceeds requirements by 11.832ns (weighted slack = -172.313ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/min_set_high__i3 (from m_clock/clk_500ms +)
Destination: FF Data in m_clock/time_min_high_i1 (to m_clock/clk_1ms +)
FF m_clock/time_min_high_i0
Delay: 7.199ns (30.8% logic, 69.2% route), 5 logic levels.
Constraint Details:
7.199ns physical path delay m_clock/SLICE_289 to m_clock/SLICE_354 exceeds
(delay constraint based on source clock period of 7.300ns and destination clock period of 4.602ns)
0.316ns delay constraint less
4.700ns skew and
0.249ns CE_SET requirement (totaling -4.633ns) by 11.832ns
Physical Path Details:
Data path m_clock/SLICE_289 to m_clock/SLICE_354:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C21A.CLK to R18C21A.Q0 m_clock/SLICE_289 (from m_clock/clk_500ms)
ROUTE 4 1.906 R18C21A.Q0 to R20C21A.A0 m_clock/min_set_high_3
CTOF_DEL --- 0.452 R20C21A.A0 to R20C21A.F0 m_clock/SLICE_963
ROUTE 1 0.885 R20C21A.F0 to R20C21D.B0 m_clock/n28
CTOF_DEL --- 0.452 R20C21D.B0 to R20C21D.F0 m_clock/SLICE_812
ROUTE 4 0.866 R20C21D.F0 to R20C20B.A0 m_clock/n25895
CTOF_DEL --- 0.452 R20C20B.A0 to R20C20B.F0 m_clock/SLICE_998
ROUTE 28 0.741 R20C20B.F0 to R19C20B.C1 m_clock/clk_1ms_enable_32
CTOF_DEL --- 0.452 R19C20B.C1 to R19C20B.F1 m_clock/SLICE_815
ROUTE 2 0.584 R19C20B.F1 to R19C20C.CE m_clock/clk_1ms_enable_27 (to m_clock/clk_1ms)
--------
7.199 (30.8% logic, 69.2% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_289:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.409 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 4.291 R4C16D.Q0 to R18C21A.CLK m_clock/clk_500ms
--------
11.691 (16.7% logic, 83.3% route), 3 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_354:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R19C20C.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Error: The following path exceeds requirements by 11.782ns (weighted slack = -171.585ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/min_set_high__i3 (from m_clock/clk_500ms +)
Destination: FF Data in m_clock/time_min_low_i0 (to m_clock/clk_1ms +)
Delay: 7.248ns (30.6% logic, 69.4% route), 5 logic levels.
Constraint Details:
7.248ns physical path delay m_clock/SLICE_289 to m_clock/SLICE_356 exceeds
(delay constraint based on source clock period of 7.300ns and destination clock period of 4.602ns)
0.316ns delay constraint less
4.700ns skew and
0.150ns DIN_SET requirement (totaling -4.534ns) by 11.782ns
Physical Path Details:
Data path m_clock/SLICE_289 to m_clock/SLICE_356:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C21A.CLK to R18C21A.Q0 m_clock/SLICE_289 (from m_clock/clk_500ms)
ROUTE 4 1.906 R18C21A.Q0 to R20C21A.A0 m_clock/min_set_high_3
CTOF_DEL --- 0.452 R20C21A.A0 to R20C21A.F0 m_clock/SLICE_963
ROUTE 1 0.885 R20C21A.F0 to R20C21D.B0 m_clock/n28
CTOF_DEL --- 0.452 R20C21D.B0 to R20C21D.F0 m_clock/SLICE_812
ROUTE 4 0.866 R20C21D.F0 to R20C20B.A0 m_clock/n25895
CTOF_DEL --- 0.452 R20C20B.A0 to R20C20B.F0 m_clock/SLICE_998
ROUTE 28 1.374 R20C20B.F0 to R20C23C.D0 m_clock/clk_1ms_enable_32
CTOF_DEL --- 0.452 R20C23C.D0 to R20C23C.F0 m_clock/SLICE_356
ROUTE 1 0.000 R20C23C.F0 to R20C23C.DI0 m_clock/time_min_low_3_N_1477_0 (to m_clock/clk_1ms)
--------
7.248 (30.6% logic, 69.4% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_289:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.409 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 4.291 R4C16D.Q0 to R18C21A.CLK m_clock/clk_500ms
--------
11.691 (16.7% logic, 83.3% route), 3 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_356:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C23C.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Error: The following path exceeds requirements by 11.782ns (weighted slack = -171.585ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/min_set_high__i3 (from m_clock/clk_500ms +)
Destination: FF Data in m_clock/time_min_low_i1 (to m_clock/clk_1ms +)
Delay: 7.248ns (30.6% logic, 69.4% route), 5 logic levels.
Constraint Details:
7.248ns physical path delay m_clock/SLICE_289 to m_clock/SLICE_356 exceeds
(delay constraint based on source clock period of 7.300ns and destination clock period of 4.602ns)
0.316ns delay constraint less
4.700ns skew and
0.150ns DIN_SET requirement (totaling -4.534ns) by 11.782ns
Physical Path Details:
Data path m_clock/SLICE_289 to m_clock/SLICE_356:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C21A.CLK to R18C21A.Q0 m_clock/SLICE_289 (from m_clock/clk_500ms)
ROUTE 4 1.906 R18C21A.Q0 to R20C21A.A0 m_clock/min_set_high_3
CTOF_DEL --- 0.452 R20C21A.A0 to R20C21A.F0 m_clock/SLICE_963
ROUTE 1 0.885 R20C21A.F0 to R20C21D.B0 m_clock/n28
CTOF_DEL --- 0.452 R20C21D.B0 to R20C21D.F0 m_clock/SLICE_812
ROUTE 4 0.866 R20C21D.F0 to R20C20B.A0 m_clock/n25895
CTOF_DEL --- 0.452 R20C20B.A0 to R20C20B.F0 m_clock/SLICE_998
ROUTE 28 1.374 R20C20B.F0 to R20C23C.D1 m_clock/clk_1ms_enable_32
CTOF_DEL --- 0.452 R20C23C.D1 to R20C23C.F1 m_clock/SLICE_356
ROUTE 1 0.000 R20C23C.F1 to R20C23C.DI1 m_clock/time_min_low_3_N_1477_1 (to m_clock/clk_1ms)
--------
7.248 (30.6% logic, 69.4% route), 5 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_289:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.409 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 4.291 R4C16D.Q0 to R18C21A.CLK m_clock/clk_500ms
--------
11.691 (16.7% logic, 83.3% route), 3 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_356:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C23C.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Warning: 5.268MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ;
1998 items scored, 1701 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 8.341ns (weighted slack = -127.383ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_low_i2 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/hour_set_low__i0 (to m_clock/clk_500ms +)
Delay: 13.271ns (31.9% logic, 68.1% route), 9 logic levels.
Constraint Details:
13.271ns physical path delay m_clock/SLICE_353 to m_clock/SLICE_282 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
0.478ns delay constraint less
-4.700ns skew and
0.248ns LSR_SET requirement (totaling 4.930ns) by 8.341ns
Physical Path Details:
Data path m_clock/SLICE_353 to m_clock/SLICE_282:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C19A.CLK to R20C19A.Q0 m_clock/SLICE_353 (from m_clock/clk_1ms)
ROUTE 14 1.500 R20C19A.Q0 to R18C19C.C0 time_hour_low_2
CTOF_DEL --- 0.452 R18C19C.C0 to R18C19C.F0 m_clock/SLICE_822
ROUTE 3 0.969 R18C19C.F0 to R20C18D.C1 n10387
CTOOFX_DEL --- 0.661 R20C18D.C1 to R20C18D.OFX0 m_clock/i1299/SLICE_451
ROUTE 1 0.541 R20C18D.OFX0 to R20C19B.D0 m_clock/n1153
CTOF_DEL --- 0.452 R20C19B.D0 to R20C19B.F0 m_clock/SLICE_818
ROUTE 4 0.683 R20C19B.F0 to R20C20C.C1 m_clock/n25510
CTOF_DEL --- 0.452 R20C20C.C1 to R20C20C.F1 m_clock/SLICE_281
ROUTE 2 1.599 R20C20C.F1 to R17C20A.A1 m_clock/n8350
CTOF_DEL --- 0.452 R17C20A.A1 to R17C20A.F1 SLICE_734
ROUTE 1 0.839 R17C20A.F1 to R18C21D.D0 m_clock/n8993
CTOF_DEL --- 0.452 R18C21D.D0 to R18C21D.F0 SLICE_363
ROUTE 1 0.873 R18C21D.F0 to R20C21B.A1 m_clock/n6_adj_1666
CTOF_DEL --- 0.452 R20C21B.A1 to R20C21B.F1 m_clock/SLICE_817
ROUTE 2 1.065 R20C21B.F1 to R18C19B.C1 m_clock/n25024
CTOF_DEL --- 0.452 R18C19B.C1 to R18C19B.F1 m_clock/SLICE_937
ROUTE 4 0.968 R18C19B.F1 to R19C19C.LSR m_clock/n12374 (to m_clock/clk_500ms)
--------
13.271 (31.9% logic, 68.1% route), 9 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_353:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C19A.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_282:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.409 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 4.291 R4C16D.Q0 to R19C19C.CLK m_clock/clk_500ms
--------
11.691 (16.7% logic, 83.3% route), 3 logic levels.
Error: The following path exceeds requirements by 8.341ns (weighted slack = -127.383ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_low_i2 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/hour_set_low__i3 (to m_clock/clk_500ms +)
Delay: 13.271ns (31.9% logic, 68.1% route), 9 logic levels.
Constraint Details:
13.271ns physical path delay m_clock/SLICE_353 to m_clock/SLICE_285 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
0.478ns delay constraint less
-4.700ns skew and
0.248ns LSR_SET requirement (totaling 4.930ns) by 8.341ns
Physical Path Details:
Data path m_clock/SLICE_353 to m_clock/SLICE_285:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C19A.CLK to R20C19A.Q0 m_clock/SLICE_353 (from m_clock/clk_1ms)
ROUTE 14 1.500 R20C19A.Q0 to R18C19C.C0 time_hour_low_2
CTOF_DEL --- 0.452 R18C19C.C0 to R18C19C.F0 m_clock/SLICE_822
ROUTE 3 0.969 R18C19C.F0 to R20C18D.C1 n10387
CTOOFX_DEL --- 0.661 R20C18D.C1 to R20C18D.OFX0 m_clock/i1299/SLICE_451
ROUTE 1 0.541 R20C18D.OFX0 to R20C19B.D0 m_clock/n1153
CTOF_DEL --- 0.452 R20C19B.D0 to R20C19B.F0 m_clock/SLICE_818
ROUTE 4 0.683 R20C19B.F0 to R20C20C.C1 m_clock/n25510
CTOF_DEL --- 0.452 R20C20C.C1 to R20C20C.F1 m_clock/SLICE_281
ROUTE 2 1.599 R20C20C.F1 to R17C20A.A1 m_clock/n8350
CTOF_DEL --- 0.452 R17C20A.A1 to R17C20A.F1 SLICE_734
ROUTE 1 0.839 R17C20A.F1 to R18C21D.D0 m_clock/n8993
CTOF_DEL --- 0.452 R18C21D.D0 to R18C21D.F0 SLICE_363
ROUTE 1 0.873 R18C21D.F0 to R20C21B.A1 m_clock/n6_adj_1666
CTOF_DEL --- 0.452 R20C21B.A1 to R20C21B.F1 m_clock/SLICE_817
ROUTE 2 1.065 R20C21B.F1 to R18C19B.C1 m_clock/n25024
CTOF_DEL --- 0.452 R18C19B.C1 to R18C19B.F1 m_clock/SLICE_937
ROUTE 4 0.968 R18C19B.F1 to R19C19D.LSR m_clock/n12374 (to m_clock/clk_500ms)
--------
13.271 (31.9% logic, 68.1% route), 9 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_353:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C19A.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_285:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.409 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 4.291 R4C16D.Q0 to R19C19D.CLK m_clock/clk_500ms
--------
11.691 (16.7% logic, 83.3% route), 3 logic levels.
Error: The following path exceeds requirements by 8.166ns (weighted slack = -124.711ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_low_i1 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/hour_set_low__i0 (to m_clock/clk_500ms +)
Delay: 13.096ns (32.3% logic, 67.7% route), 9 logic levels.
Constraint Details:
13.096ns physical path delay m_clock/SLICE_352 to m_clock/SLICE_282 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
0.478ns delay constraint less
-4.700ns skew and
0.248ns LSR_SET requirement (totaling 4.930ns) by 8.166ns
Physical Path Details:
Data path m_clock/SLICE_352 to m_clock/SLICE_282:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C19D.CLK to R20C19D.Q1 m_clock/SLICE_352 (from m_clock/clk_1ms)
ROUTE 15 1.325 R20C19D.Q1 to R18C19C.B0 time_hour_low_1
CTOF_DEL --- 0.452 R18C19C.B0 to R18C19C.F0 m_clock/SLICE_822
ROUTE 3 0.969 R18C19C.F0 to R20C18D.C1 n10387
CTOOFX_DEL --- 0.661 R20C18D.C1 to R20C18D.OFX0 m_clock/i1299/SLICE_451
ROUTE 1 0.541 R20C18D.OFX0 to R20C19B.D0 m_clock/n1153
CTOF_DEL --- 0.452 R20C19B.D0 to R20C19B.F0 m_clock/SLICE_818
ROUTE 4 0.683 R20C19B.F0 to R20C20C.C1 m_clock/n25510
CTOF_DEL --- 0.452 R20C20C.C1 to R20C20C.F1 m_clock/SLICE_281
ROUTE 2 1.599 R20C20C.F1 to R17C20A.A1 m_clock/n8350
CTOF_DEL --- 0.452 R17C20A.A1 to R17C20A.F1 SLICE_734
ROUTE 1 0.839 R17C20A.F1 to R18C21D.D0 m_clock/n8993
CTOF_DEL --- 0.452 R18C21D.D0 to R18C21D.F0 SLICE_363
ROUTE 1 0.873 R18C21D.F0 to R20C21B.A1 m_clock/n6_adj_1666
CTOF_DEL --- 0.452 R20C21B.A1 to R20C21B.F1 m_clock/SLICE_817
ROUTE 2 1.065 R20C21B.F1 to R18C19B.C1 m_clock/n25024
CTOF_DEL --- 0.452 R18C19B.C1 to R18C19B.F1 m_clock/SLICE_937
ROUTE 4 0.968 R18C19B.F1 to R19C19C.LSR m_clock/n12374 (to m_clock/clk_500ms)
--------
13.096 (32.3% logic, 67.7% route), 9 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_352:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C19D.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_282:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.409 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 4.291 R4C16D.Q0 to R19C19C.CLK m_clock/clk_500ms
--------
11.691 (16.7% logic, 83.3% route), 3 logic levels.
Error: The following path exceeds requirements by 8.166ns (weighted slack = -124.711ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_low_i1 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/hour_set_low__i3 (to m_clock/clk_500ms +)
Delay: 13.096ns (32.3% logic, 67.7% route), 9 logic levels.
Constraint Details:
13.096ns physical path delay m_clock/SLICE_352 to m_clock/SLICE_285 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
0.478ns delay constraint less
-4.700ns skew and
0.248ns LSR_SET requirement (totaling 4.930ns) by 8.166ns
Physical Path Details:
Data path m_clock/SLICE_352 to m_clock/SLICE_285:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C19D.CLK to R20C19D.Q1 m_clock/SLICE_352 (from m_clock/clk_1ms)
ROUTE 15 1.325 R20C19D.Q1 to R18C19C.B0 time_hour_low_1
CTOF_DEL --- 0.452 R18C19C.B0 to R18C19C.F0 m_clock/SLICE_822
ROUTE 3 0.969 R18C19C.F0 to R20C18D.C1 n10387
CTOOFX_DEL --- 0.661 R20C18D.C1 to R20C18D.OFX0 m_clock/i1299/SLICE_451
ROUTE 1 0.541 R20C18D.OFX0 to R20C19B.D0 m_clock/n1153
CTOF_DEL --- 0.452 R20C19B.D0 to R20C19B.F0 m_clock/SLICE_818
ROUTE 4 0.683 R20C19B.F0 to R20C20C.C1 m_clock/n25510
CTOF_DEL --- 0.452 R20C20C.C1 to R20C20C.F1 m_clock/SLICE_281
ROUTE 2 1.599 R20C20C.F1 to R17C20A.A1 m_clock/n8350
CTOF_DEL --- 0.452 R17C20A.A1 to R17C20A.F1 SLICE_734
ROUTE 1 0.839 R17C20A.F1 to R18C21D.D0 m_clock/n8993
CTOF_DEL --- 0.452 R18C21D.D0 to R18C21D.F0 SLICE_363
ROUTE 1 0.873 R18C21D.F0 to R20C21B.A1 m_clock/n6_adj_1666
CTOF_DEL --- 0.452 R20C21B.A1 to R20C21B.F1 m_clock/SLICE_817
ROUTE 2 1.065 R20C21B.F1 to R18C19B.C1 m_clock/n25024
CTOF_DEL --- 0.452 R18C19B.C1 to R18C19B.F1 m_clock/SLICE_937
ROUTE 4 0.968 R18C19B.F1 to R19C19D.LSR m_clock/n12374 (to m_clock/clk_500ms)
--------
13.096 (32.3% logic, 67.7% route), 9 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_352:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C19D.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_285:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.409 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 4.291 R4C16D.Q0 to R19C19D.CLK m_clock/clk_500ms
--------
11.691 (16.7% logic, 83.3% route), 3 logic levels.
Error: The following path exceeds requirements by 8.120ns (weighted slack = -124.008ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_low_i1 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/hour_set_low__i0 (to m_clock/clk_500ms +)
Delay: 13.050ns (30.8% logic, 69.2% route), 9 logic levels.
Constraint Details:
13.050ns physical path delay m_clock/SLICE_352 to m_clock/SLICE_282 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
0.478ns delay constraint less
-4.700ns skew and
0.248ns LSR_SET requirement (totaling 4.930ns) by 8.120ns
Physical Path Details:
Data path m_clock/SLICE_352 to m_clock/SLICE_282:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C19D.CLK to R20C19D.Q1 m_clock/SLICE_352 (from m_clock/clk_1ms)
ROUTE 15 0.873 R20C19D.Q1 to R20C19B.A1 time_hour_low_1
CTOF_DEL --- 0.452 R20C19B.A1 to R20C19B.F1 m_clock/SLICE_818
ROUTE 4 1.343 R20C19B.F1 to R20C20A.D1 m_clock/n27719
CTOF_DEL --- 0.452 R20C20A.D1 to R20C20A.F1 m_clock/SLICE_804
ROUTE 7 0.580 R20C20A.F1 to R20C20D.D0 m_clock/n27596
CTOF_DEL --- 0.452 R20C20D.D0 to R20C20D.F0 m_clock/SLICE_936
ROUTE 1 0.885 R20C20D.F0 to R20C20C.B1 m_clock/n27776
CTOF_DEL --- 0.452 R20C20C.B1 to R20C20C.F1 m_clock/SLICE_281
ROUTE 2 1.599 R20C20C.F1 to R17C20A.A1 m_clock/n8350
CTOF_DEL --- 0.452 R17C20A.A1 to R17C20A.F1 SLICE_734
ROUTE 1 0.839 R17C20A.F1 to R18C21D.D0 m_clock/n8993
CTOF_DEL --- 0.452 R18C21D.D0 to R18C21D.F0 SLICE_363
ROUTE 1 0.873 R18C21D.F0 to R20C21B.A1 m_clock/n6_adj_1666
CTOF_DEL --- 0.452 R20C21B.A1 to R20C21B.F1 m_clock/SLICE_817
ROUTE 2 1.065 R20C21B.F1 to R18C19B.C1 m_clock/n25024
CTOF_DEL --- 0.452 R18C19B.C1 to R18C19B.F1 m_clock/SLICE_937
ROUTE 4 0.968 R18C19B.F1 to R19C19C.LSR m_clock/n12374 (to m_clock/clk_500ms)
--------
13.050 (30.8% logic, 69.2% route), 9 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_352:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C19D.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_282:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.409 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 4.291 R4C16D.Q0 to R19C19C.CLK m_clock/clk_500ms
--------
11.691 (16.7% logic, 83.3% route), 3 logic levels.
Error: The following path exceeds requirements by 8.120ns (weighted slack = -124.008ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_low_i1 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/hour_set_low__i3 (to m_clock/clk_500ms +)
Delay: 13.050ns (30.8% logic, 69.2% route), 9 logic levels.
Constraint Details:
13.050ns physical path delay m_clock/SLICE_352 to m_clock/SLICE_285 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
0.478ns delay constraint less
-4.700ns skew and
0.248ns LSR_SET requirement (totaling 4.930ns) by 8.120ns
Physical Path Details:
Data path m_clock/SLICE_352 to m_clock/SLICE_285:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C19D.CLK to R20C19D.Q1 m_clock/SLICE_352 (from m_clock/clk_1ms)
ROUTE 15 0.873 R20C19D.Q1 to R20C19B.A1 time_hour_low_1
CTOF_DEL --- 0.452 R20C19B.A1 to R20C19B.F1 m_clock/SLICE_818
ROUTE 4 1.343 R20C19B.F1 to R20C20A.D1 m_clock/n27719
CTOF_DEL --- 0.452 R20C20A.D1 to R20C20A.F1 m_clock/SLICE_804
ROUTE 7 0.580 R20C20A.F1 to R20C20D.D0 m_clock/n27596
CTOF_DEL --- 0.452 R20C20D.D0 to R20C20D.F0 m_clock/SLICE_936
ROUTE 1 0.885 R20C20D.F0 to R20C20C.B1 m_clock/n27776
CTOF_DEL --- 0.452 R20C20C.B1 to R20C20C.F1 m_clock/SLICE_281
ROUTE 2 1.599 R20C20C.F1 to R17C20A.A1 m_clock/n8350
CTOF_DEL --- 0.452 R17C20A.A1 to R17C20A.F1 SLICE_734
ROUTE 1 0.839 R17C20A.F1 to R18C21D.D0 m_clock/n8993
CTOF_DEL --- 0.452 R18C21D.D0 to R18C21D.F0 SLICE_363
ROUTE 1 0.873 R18C21D.F0 to R20C21B.A1 m_clock/n6_adj_1666
CTOF_DEL --- 0.452 R20C21B.A1 to R20C21B.F1 m_clock/SLICE_817
ROUTE 2 1.065 R20C21B.F1 to R18C19B.C1 m_clock/n25024
CTOF_DEL --- 0.452 R18C19B.C1 to R18C19B.F1 m_clock/SLICE_937
ROUTE 4 0.968 R18C19B.F1 to R19C19D.LSR m_clock/n12374 (to m_clock/clk_500ms)
--------
13.050 (30.8% logic, 69.2% route), 9 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_352:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C19D.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_285:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.409 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 4.291 R4C16D.Q0 to R19C19D.CLK m_clock/clk_500ms
--------
11.691 (16.7% logic, 83.3% route), 3 logic levels.
Error: The following path exceeds requirements by 7.958ns (weighted slack = -121.534ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_low_i2 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/hour_set_low__i2 (to m_clock/clk_500ms +)
Delay: 12.888ns (32.9% logic, 67.1% route), 9 logic levels.
Constraint Details:
12.888ns physical path delay m_clock/SLICE_353 to m_clock/SLICE_284 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
0.478ns delay constraint less
-4.700ns skew and
0.248ns LSR_SET requirement (totaling 4.930ns) by 7.958ns
Physical Path Details:
Data path m_clock/SLICE_353 to m_clock/SLICE_284:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C19A.CLK to R20C19A.Q0 m_clock/SLICE_353 (from m_clock/clk_1ms)
ROUTE 14 1.500 R20C19A.Q0 to R18C19C.C0 time_hour_low_2
CTOF_DEL --- 0.452 R18C19C.C0 to R18C19C.F0 m_clock/SLICE_822
ROUTE 3 0.969 R18C19C.F0 to R20C18D.C1 n10387
CTOOFX_DEL --- 0.661 R20C18D.C1 to R20C18D.OFX0 m_clock/i1299/SLICE_451
ROUTE 1 0.541 R20C18D.OFX0 to R20C19B.D0 m_clock/n1153
CTOF_DEL --- 0.452 R20C19B.D0 to R20C19B.F0 m_clock/SLICE_818
ROUTE 4 0.683 R20C19B.F0 to R20C20C.C1 m_clock/n25510
CTOF_DEL --- 0.452 R20C20C.C1 to R20C20C.F1 m_clock/SLICE_281
ROUTE 2 1.599 R20C20C.F1 to R17C20A.A1 m_clock/n8350
CTOF_DEL --- 0.452 R17C20A.A1 to R17C20A.F1 SLICE_734
ROUTE 1 0.839 R17C20A.F1 to R18C21D.D0 m_clock/n8993
CTOF_DEL --- 0.452 R18C21D.D0 to R18C21D.F0 SLICE_363
ROUTE 1 0.873 R18C21D.F0 to R20C21B.A1 m_clock/n6_adj_1666
CTOF_DEL --- 0.452 R20C21B.A1 to R20C21B.F1 m_clock/SLICE_817
ROUTE 2 1.065 R20C21B.F1 to R18C19B.C1 m_clock/n25024
CTOF_DEL --- 0.452 R18C19B.C1 to R18C19B.F1 m_clock/SLICE_937
ROUTE 4 0.585 R18C19B.F1 to R18C19D.LSR m_clock/n12374 (to m_clock/clk_500ms)
--------
12.888 (32.9% logic, 67.1% route), 9 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_353:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C19A.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_284:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.409 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 4.291 R4C16D.Q0 to R18C19D.CLK m_clock/clk_500ms
--------
11.691 (16.7% logic, 83.3% route), 3 logic levels.
Error: The following path exceeds requirements by 7.958ns (weighted slack = -121.534ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_low_i2 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/hour_set_low__i1 (to m_clock/clk_500ms +)
Delay: 12.888ns (32.9% logic, 67.1% route), 9 logic levels.
Constraint Details:
12.888ns physical path delay m_clock/SLICE_353 to m_clock/SLICE_283 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
0.478ns delay constraint less
-4.700ns skew and
0.248ns LSR_SET requirement (totaling 4.930ns) by 7.958ns
Physical Path Details:
Data path m_clock/SLICE_353 to m_clock/SLICE_283:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C19A.CLK to R20C19A.Q0 m_clock/SLICE_353 (from m_clock/clk_1ms)
ROUTE 14 1.500 R20C19A.Q0 to R18C19C.C0 time_hour_low_2
CTOF_DEL --- 0.452 R18C19C.C0 to R18C19C.F0 m_clock/SLICE_822
ROUTE 3 0.969 R18C19C.F0 to R20C18D.C1 n10387
CTOOFX_DEL --- 0.661 R20C18D.C1 to R20C18D.OFX0 m_clock/i1299/SLICE_451
ROUTE 1 0.541 R20C18D.OFX0 to R20C19B.D0 m_clock/n1153
CTOF_DEL --- 0.452 R20C19B.D0 to R20C19B.F0 m_clock/SLICE_818
ROUTE 4 0.683 R20C19B.F0 to R20C20C.C1 m_clock/n25510
CTOF_DEL --- 0.452 R20C20C.C1 to R20C20C.F1 m_clock/SLICE_281
ROUTE 2 1.599 R20C20C.F1 to R17C20A.A1 m_clock/n8350
CTOF_DEL --- 0.452 R17C20A.A1 to R17C20A.F1 SLICE_734
ROUTE 1 0.839 R17C20A.F1 to R18C21D.D0 m_clock/n8993
CTOF_DEL --- 0.452 R18C21D.D0 to R18C21D.F0 SLICE_363
ROUTE 1 0.873 R18C21D.F0 to R20C21B.A1 m_clock/n6_adj_1666
CTOF_DEL --- 0.452 R20C21B.A1 to R20C21B.F1 m_clock/SLICE_817
ROUTE 2 1.065 R20C21B.F1 to R18C19B.C1 m_clock/n25024
CTOF_DEL --- 0.452 R18C19B.C1 to R18C19B.F1 m_clock/SLICE_937
ROUTE 4 0.585 R18C19B.F1 to R18C19A.LSR m_clock/n12374 (to m_clock/clk_500ms)
--------
12.888 (32.9% logic, 67.1% route), 9 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_353:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C19A.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_283:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.409 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 4.291 R4C16D.Q0 to R18C19A.CLK m_clock/clk_500ms
--------
11.691 (16.7% logic, 83.3% route), 3 logic levels.
Error: The following path exceeds requirements by 7.822ns (weighted slack = -119.457ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_low_i2 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/hour_set_low__i0 (to m_clock/clk_500ms +)
Delay: 12.752ns (31.6% logic, 68.4% route), 9 logic levels.
Constraint Details:
12.752ns physical path delay m_clock/SLICE_353 to m_clock/SLICE_282 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
0.478ns delay constraint less
-4.700ns skew and
0.248ns LSR_SET requirement (totaling 4.930ns) by 7.822ns
Physical Path Details:
Data path m_clock/SLICE_353 to m_clock/SLICE_282:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C19A.CLK to R20C19A.Q0 m_clock/SLICE_353 (from m_clock/clk_1ms)
ROUTE 14 0.575 R20C19A.Q0 to R20C19B.D1 time_hour_low_2
CTOF_DEL --- 0.452 R20C19B.D1 to R20C19B.F1 m_clock/SLICE_818
ROUTE 4 1.343 R20C19B.F1 to R20C20A.D1 m_clock/n27719
CTOF_DEL --- 0.452 R20C20A.D1 to R20C20A.F1 m_clock/SLICE_804
ROUTE 7 0.580 R20C20A.F1 to R20C20D.D0 m_clock/n27596
CTOF_DEL --- 0.452 R20C20D.D0 to R20C20D.F0 m_clock/SLICE_936
ROUTE 1 0.885 R20C20D.F0 to R20C20C.B1 m_clock/n27776
CTOF_DEL --- 0.452 R20C20C.B1 to R20C20C.F1 m_clock/SLICE_281
ROUTE 2 1.599 R20C20C.F1 to R17C20A.A1 m_clock/n8350
CTOF_DEL --- 0.452 R17C20A.A1 to R17C20A.F1 SLICE_734
ROUTE 1 0.839 R17C20A.F1 to R18C21D.D0 m_clock/n8993
CTOF_DEL --- 0.452 R18C21D.D0 to R18C21D.F0 SLICE_363
ROUTE 1 0.873 R18C21D.F0 to R20C21B.A1 m_clock/n6_adj_1666
CTOF_DEL --- 0.452 R20C21B.A1 to R20C21B.F1 m_clock/SLICE_817
ROUTE 2 1.065 R20C21B.F1 to R18C19B.C1 m_clock/n25024
CTOF_DEL --- 0.452 R18C19B.C1 to R18C19B.F1 m_clock/SLICE_937
ROUTE 4 0.968 R18C19B.F1 to R19C19C.LSR m_clock/n12374 (to m_clock/clk_500ms)
--------
12.752 (31.6% logic, 68.4% route), 9 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_353:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C19A.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_282:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.409 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 4.291 R4C16D.Q0 to R19C19C.CLK m_clock/clk_500ms
--------
11.691 (16.7% logic, 83.3% route), 3 logic levels.
Error: The following path exceeds requirements by 7.822ns (weighted slack = -119.457ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_low_i2 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/hour_set_low__i3 (to m_clock/clk_500ms +)
Delay: 12.752ns (31.6% logic, 68.4% route), 9 logic levels.
Constraint Details:
12.752ns physical path delay m_clock/SLICE_353 to m_clock/SLICE_285 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
0.478ns delay constraint less
-4.700ns skew and
0.248ns LSR_SET requirement (totaling 4.930ns) by 7.822ns
Physical Path Details:
Data path m_clock/SLICE_353 to m_clock/SLICE_285:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C19A.CLK to R20C19A.Q0 m_clock/SLICE_353 (from m_clock/clk_1ms)
ROUTE 14 0.575 R20C19A.Q0 to R20C19B.D1 time_hour_low_2
CTOF_DEL --- 0.452 R20C19B.D1 to R20C19B.F1 m_clock/SLICE_818
ROUTE 4 1.343 R20C19B.F1 to R20C20A.D1 m_clock/n27719
CTOF_DEL --- 0.452 R20C20A.D1 to R20C20A.F1 m_clock/SLICE_804
ROUTE 7 0.580 R20C20A.F1 to R20C20D.D0 m_clock/n27596
CTOF_DEL --- 0.452 R20C20D.D0 to R20C20D.F0 m_clock/SLICE_936
ROUTE 1 0.885 R20C20D.F0 to R20C20C.B1 m_clock/n27776
CTOF_DEL --- 0.452 R20C20C.B1 to R20C20C.F1 m_clock/SLICE_281
ROUTE 2 1.599 R20C20C.F1 to R17C20A.A1 m_clock/n8350
CTOF_DEL --- 0.452 R17C20A.A1 to R17C20A.F1 SLICE_734
ROUTE 1 0.839 R17C20A.F1 to R18C21D.D0 m_clock/n8993
CTOF_DEL --- 0.452 R18C21D.D0 to R18C21D.F0 SLICE_363
ROUTE 1 0.873 R18C21D.F0 to R20C21B.A1 m_clock/n6_adj_1666
CTOF_DEL --- 0.452 R20C21B.A1 to R20C21B.F1 m_clock/SLICE_817
ROUTE 2 1.065 R20C21B.F1 to R18C19B.C1 m_clock/n25024
CTOF_DEL --- 0.452 R18C19B.C1 to R18C19B.F1 m_clock/SLICE_937
ROUTE 4 0.968 R18C19B.F1 to R19C19D.LSR m_clock/n12374 (to m_clock/clk_500ms)
--------
12.752 (31.6% logic, 68.4% route), 9 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_353:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R20C19A.CLK m_clock/clk_1ms
--------
6.991 (22.0% logic, 78.0% route), 2 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_285:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.409 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 2.660 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.409 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 4.291 R4C16D.Q0 to R19C19D.CLK m_clock/clk_500ms
--------
11.691 (16.7% logic, 83.3% route), 3 logic levels.
Warning: 7.425MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "m_DS18B20Z/clk_1mhz" 293.858000 MHz ;
59 items scored, 58 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 2.731ns (weighted slack = -16.276ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_wr_buffer_i0_i4 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/one_wire_buffer_155 (to m_DS18B20Z/clk_1mhz +)
Delay: 4.788ns (41.2% logic, 58.8% route), 4 logic levels.
Constraint Details:
4.788ns physical path delay m_DS18B20Z/SLICE_853 to m_DS18B20Z/SLICE_340 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
0.571ns delay constraint less
-1.636ns skew and
0.150ns DIN_SET requirement (totaling 2.057ns) by 2.731ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_853 to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R19C7A.CLK to R19C7A.Q0 m_DS18B20Z/SLICE_853 (from sys_clk_c)
ROUTE 1 1.254 R19C7A.Q0 to R19C6A.B0 m_DS18B20Z/data_wr_buffer_4
CTOOFX_DEL --- 0.661 R19C6A.B0 to R19C6A.OFX0 m_DS18B20Z/i24355/SLICE_460
ROUTE 1 0.678 R19C6A.OFX0 to R19C4A.C1 m_DS18B20Z/one_wire_N_281
CTOF_DEL --- 0.452 R19C4A.C1 to R19C4A.F1 m_DS18B20Z/SLICE_974
ROUTE 1 0.882 R19C4A.F1 to R18C4D.B0 m_DS18B20Z/n10
CTOF_DEL --- 0.452 R18C4D.B0 to R18C4D.F0 m_DS18B20Z/SLICE_340
ROUTE 1 0.000 R18C4D.F0 to R18C4D.DI0 m_DS18B20Z/one_wire_N_277 (to m_DS18B20Z/clk_1mhz)
--------
4.788 (41.2% logic, 58.8% route), 4 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_853:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R19C7A.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Destination Clock Path sys_clk to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R20C5A.CLK sys_clk_c
REG_DEL --- 0.409 R20C5A.CLK to R20C5A.Q0 m_DS18B20Z/SLICE_145
ROUTE 12 1.227 R20C5A.Q0 to R18C4D.CLK m_DS18B20Z/clk_1mhz
--------
5.558 (27.7% logic, 72.3% route), 2 logic levels.
Error: The following path exceeds requirements by 2.700ns (weighted slack = -16.091ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_wr_buffer_i0_i7 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/one_wire_buffer_155 (to m_DS18B20Z/clk_1mhz +)
Delay: 4.757ns (41.5% logic, 58.5% route), 4 logic levels.
Constraint Details:
4.757ns physical path delay m_DS18B20Z/SLICE_868 to m_DS18B20Z/SLICE_340 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
0.571ns delay constraint less
-1.636ns skew and
0.150ns DIN_SET requirement (totaling 2.057ns) by 2.700ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_868 to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R19C7B.CLK to R19C7B.Q0 m_DS18B20Z/SLICE_868 (from sys_clk_c)
ROUTE 1 1.223 R19C7B.Q0 to R19C6A.A1 m_DS18B20Z/data_wr_buffer_7
CTOOFX_DEL --- 0.661 R19C6A.A1 to R19C6A.OFX0 m_DS18B20Z/i24355/SLICE_460
ROUTE 1 0.678 R19C6A.OFX0 to R19C4A.C1 m_DS18B20Z/one_wire_N_281
CTOF_DEL --- 0.452 R19C4A.C1 to R19C4A.F1 m_DS18B20Z/SLICE_974
ROUTE 1 0.882 R19C4A.F1 to R18C4D.B0 m_DS18B20Z/n10
CTOF_DEL --- 0.452 R18C4D.B0 to R18C4D.F0 m_DS18B20Z/SLICE_340
ROUTE 1 0.000 R18C4D.F0 to R18C4D.DI0 m_DS18B20Z/one_wire_N_277 (to m_DS18B20Z/clk_1mhz)
--------
4.757 (41.5% logic, 58.5% route), 4 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_868:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R19C7B.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Destination Clock Path sys_clk to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R20C5A.CLK sys_clk_c
REG_DEL --- 0.409 R20C5A.CLK to R20C5A.Q0 m_DS18B20Z/SLICE_145
ROUTE 12 1.227 R20C5A.Q0 to R18C4D.CLK m_DS18B20Z/clk_1mhz
--------
5.558 (27.7% logic, 72.3% route), 2 logic levels.
Error: The following path exceeds requirements by 2.685ns (weighted slack = -16.002ns)