| Methods' Details |
startDocument
- Description
- receives notification of the beginning of a document.
|
|
endDocument
- Description
- receives notification of the end of a document.
|
|
startElement
- Description
- receives notification of the beginning of an element .
|
|
endElement
| void |
| endElement( |
[in] string |
aName ) |
| raises( |
SAXException ); |
- Description
- receives notification of the end of an element.
|
|
characters
| void |
| characters( |
[in] string |
aChars ) |
| raises( |
SAXException ); |
- Description
- receives notification of character data.
|
|
ignorableWhitespace
| void |
| ignorableWhitespace( |
[in] string |
aWhitespaces ) |
| raises( |
SAXException ); |
- Description
- receives notification of white space that can be ignored.
|
|
processingInstruction
| void |
| processingInstruction( |
[in] string |
aTarget, |
| [in] string |
aData ) |
| raises( |
SAXException ); |
- Description
- receives notification of a processing instruction.
|
|
setDocumentLocator
- Description
- receives an object for locating the origin of SAX document events.
|
|
Copyright © 2013, The Apache Software Foundation, Licensed under the Apache License, Version 2.0. Apache, the Apache feather logo, Apache OpenOffice and OpenOffice.org are trademarks of The Apache Software Foundation. Other names may be trademarks of their respective owners.


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Intel® Accelerator Functional Unit (AFU) Simulation Environment (ASE) User Guide¶
Intended Audience¶
The Accelerator Functional Unit (AFU) Accelerator Simulation Environment (ASE) User Guide addresses both beginning and experienced developers. To be successful, you should have knowledge and experience in the following areas:
C/C++
Verilog/SystemVerilog
RTL simulators such as Synopsys VCS-MX* or Mentor Graphics ModelSim-SE* or QuestaSim*
Alternatively, you can create a team that includes developers who specialize in either RTL or software development. Previous FPGA place and route (PAR) experience is not required to be successful, but PAR experience is also a useful skill.
Introduction¶
The ASE provides a consistent transaction-level hardware interface and software API that allows you to develop a production-quality Accelerated Functional Unit (AFU) and host software application. The ASE supports both the Intel Xeon® Processor with Integrated FPGA and the Intel Acceleration Stack for Intel Xeon CPU with FPGAs also called the Intel Programmable Acceleration Card (PAC). The figures in this user guide illustrate the Intel PAC with Arria® 10 GX FPGA. The figures show a local memory that is only available on the PAC.
To use the ASE Environment you must have source code in a language that RTL simulators can interpret. The following languages are possible:
Verilog
SystemVerilog
VHDL
Note
The ASE supports one AFU and one application at a time. The ASE does not support multiple-slot simulation.
AFU Simulation Environment (ASE) Overview¶
ASE is a dual-process simulator. One process runs an AFU RTL simulation. The other process connects to software that runs on the RTL AFU simulation. This unified simulation environment reduces AFU hardware and software development time. The OPAE software distribution includes the ASE.
The ASE provides two interfaces:
Software: OPAE API implemented in the C programming language.
Hardware: Core Cache Interface (CCI-P) specification implemented in SystemVerilog.
Use these interfaces to deploy your IP on the Integrated FPGA Platform or the Intel PAC with Arria 10 GX FPGA.
ASE Capabilities¶
The ASE provides a protocol checker to ensure protocol correctness. The ASE also provides methods to identify potential issues early, before in-system deployment.
The ASE can help identify certain lock conditions and Configuration and Status Registers (CSR) address mapping and pointer math errors.
The ASE tracks memory requested from the accelerator. The memory model immediately flags illegal memory transactions to locations outside of requested memory spaces. Consequently, you can fix incorrect memory accesses early, during the simulation phase.
The ASE does not guarantee that you can synthesize an AFU. After you verify the AFU RTL functionality in the ASE, use the ASE and the Intel Quartus® Prime Pro Edition software iteratively to generate the Accelerator Function (AF).
The ASE provides a data hazard checker that identifies CCI-P traffic patterns that may cause Write After Write (WAW), Read After Write (RAW), and Write After Read (WAR) hazards. Debug these transactions using a waveform viewer or avoid them by using a relevant Memory Properties Factory (MPF) shim.
The ASE does not require administrator privileges. After installing all the required tools, you can run the ASE on a plain vanilla user Linux machine.
ASE Limitations¶
When using ASE in the application development cycle, consider the following limitations:
The ASE is a transaction-level simulator. It does not model either Intel UPI- or PCIe-specific packet structures and protocol layers.
The ASE does not simulate caching and is not a cache simulator. It cannot reliably simulate cache collisions or capacity issues.
Although ASE models some latency parameters, it cannot model real-time system-specific latency. It is also not an accurate timing simulation of the design or latency and bandwidth of the real system. The ASE models enable you to develop functionally correct accelerators.
The ASE does not simulate multi-AFU or multi-socket configurations.
ASE-Based AFU Design Workflow¶
AFU development using the ASE includes the following four stages:
Learning/Training: Learn to use ASE and understand the interface specifications and platform. Review sample code to get an understanding of the CCI-P specification and OPAE API function calls. Run samples in an ASE simulation.
Development Phase: Use the ASE to develop AFU RTL and software application in a single workflow. Develop RTL from the specification or by modifying existing sample RTL. The ASE includes a behavioral model of the FPGA Interface Manager (FIM) IP that provides immediate feedback on functionality during the development phase. The ASE flags errors in CCI-P protocols, transactions, and memory accesses. Consequently, you can fix these errors before moving to the time-consuming bitstream generation phase.
Bitstream Generation: Once AFU RTL and software are functionally correct, open the AFU RTL in the Intel Quartus Prime Pro Edition software. Run the place and route (PAR) tools for your platform.
Use the Synthesis reports to correct problems in the AFU RTL. Then, return to the development phase and revalidate in ASE. Bitstream generation can take hours depending on design complexity, area, and so on. After successful bitstream generation, perform timing analysis to check for timing corners, setup and hold violations, clock closure, and so on. After correcting failures found during timing analysis, revalidate in the ASE environment. When the AFU is error-free, generate the Accelerator Function (AF) bitstream that represents the AFU.
In-system Deployment: Test the AF in system hardware. Use Signal Tap to debug problems. Develop platform-specific software optimizations.
The AFU RTL code and OPAE software code you create in the ASE is compatible with the Intel Quartus Prime PAR software if the following two conditions are true:
The AFU RTL code is synthesizable.
The AFU RTL code meets timing.
In the simulation environment, complete the following steps to create an AF bitstream and program the hardware:
Compile the AFU RTL in either the Synopsys VCS-MX or in the Mentor Graphics ModelSim-SE or QuestaSim simulators.
Compile the software application for an ASE-specific implementation of the OPAE API.
Synthesize the AFU RTL in the Intel Quartus Prime Pro software to generate a bitstream.
Program the hardware using this bitstream.
Note
The ASE only operates using the AFU RTL source code. It cannot take the AF bitstream as input.
System Requirements¶
The OPAE software release includes the ASE. The current OPAE ASE release supports both Acceleration Stack for the Intel Xeon Processor with Integrated FPGA and Acceleration Stack for the Intel PAC card.
The ASE is available only on 64-bit Linux operating systems with one of the following simulators:
64-bit Synopsys* RTL Simulator (minimum version VCS-MX H2013.06-SP1)
32 and 64-bit Mentor Graphics* Modelsim SE Simulator (minimum version 10.5a)
64-bit Mentor Graphics* QuestaSim Simulator (minimum version 10.4d)
ASE performance is better on a 64-bit RTL simulator. Consult your RTL simulator vendor for Synopsys or Mentor Graphics for specific simulation requirements.
The ASE uses Inter-Process Communication (IPC) constructs. Under most circumstances these constructs operate without glitches.
The following Linux locations should exist and be writeable. In most Linux distributions, /dev/shm
comes pre-mounted as a
default option.
Here are the other ASE requirements:
C-Compiler: gcc 4.8.5 or above
Boost Development libraries
UUID Development libraries
JSON Development libraries
Please see the dependencies of the OPAE System library build process
CMake: version 2.8.11 or above
GLIBC: version 2.19 or above
Python: version 2.7 or above
Intel Quartus Prime Pro Edition: The ASE must find the
$QUARTUS_HOME/eda/sim_lib/
directory. You specify this directory during project definition in the Intel Quartus Prime Pro Edition software.
The ASE provides the env_check.sh
bash script in the /sw/opae-x.x.x/ase/scripts
directory. Run this script to
verify the your installation.
Check the RTL simulator product information for supported operating systems, installation notes, and other related information. The RTL simulator must be able to perform the following functions:
Compilation of the SystemVerilog Direct Programming Interface (DPI) constructs
Compilation of the standard examples that are included in the installation
Support for SystemC
Package Description¶
Download the ASE as source or in RPM format.
The source directory tree is:
OPAE_BASEDIR
|-- ase
| |-- api
| | -- src
| |-- in
| |-- rtl
| | -- dcp_emif_model
| |-- scripts
| |-- sw
|
|-- cmake
|-- common
| |-- include
| | |-- opae
| | |--safe_string
|
|-- doc
|-- libopae
|-- libopaecxx
|-- platforms
|-- pyopae
|-- safe_string
|-- samples
|-- scripts
|-- tools
This directory tree shows the package structure of the ASE distribution. The following directories implement and run the ASE simulator:
ase
: This is the ASE simulator implementation directory. It contains the following subdirectories:api/src
: This directory contains the OPAE Intel ASE implementation as a compiled library. You can link statically or dynamically to this library.rtl
: This directory contains the RTL components of the ASE. You can compile this RTL for either platform.dcp_emif_model
: This is the local DDR memory model for PAC card. Compile this model for PAC mode simulations.
scripts
: This directory contains several useful scripts. Refer to the ASE Scripts Section for more information.sw
: This directory contains the software components of the ASE. All simulations require the software components. The GNU Compiler Collection (GCC) compiles these components.
common
: This directory contains the OPAE library definitions. It defines various macros for access to an FPGA in an OPAE context.libopae
: This library is the Intel platform-specific implementation of the OPAE API.platforms
: This directory contains scripts and RTL to manage the connection between a platform and the AFU top-level interface.scripts
: This directory contains test build scripts.tools
: This directory contains the FPGA tools including the fpgadiag and fpgaconfig tools.
ASE Scripts¶
The ASE distribution under the ase/scripts
includes several scripts. Use these scripts to initialize, set up,
and clean an existing ASE simulation environment.
Simulation Tool Set Up¶
Use ase/scripts/ase_setup_template.sh
as a template script to set up the required tools. This script has many empty
placeholders for site- and environment-specific information. Consult your Electronic Design Automation (EDA) tools administrator,
or the RTL simulator user guides for help setting up the tools.
ASE Environment Check¶
This script checks the status of the OS distribution, distro, and available system libraries. This check is a non-exhaustive. It looks for only the most important dependencies, such as the GCC version, GLIBC version, and so on.
$ ./ase/scripts/env_check.sh
AFU Simulation Using the ASE¶
Before configuring the ASE, follow the instructions for building the OPAE SDK and ensure that either the OPAE
installed bin
or the OPAE build tree bin
directory is on your shell’s PATH
.
To simulate an AFU, replicate the ASE source tree and add the AFU-specific configuration. The OPAE installation includes
several scripts to accomplish this task. The primary script, afu_sim_setup
, is in the OPAE bin
directory.
Refer to the ASE Example section below for a sample workload definition and execution flow.
afu_sim_setup¶
The afu_sim_setup
script reads a file containing a list of RTL sources (<rtl_sources.txt>) and configures a simulation
environment for the specified sources. The afu_sim_setup
command copies your base ASE environment to the <target dir>.
$ afu_sim_setup --sources=<rtl_sources.txt> <target dir>
The only required argument to the
afu_sim_setup
command is the directory for the new AFU environment. Here are the optional arguments:--help
Thehelp
argument lists all the arguments toafu_sim_setup
.--platform
: Theplatform
argument specifies any platform defined in the platform database, including both the Integrated FPGA Platform or the Intel PAC. This argument is generally not required when a hardware platform release is installed. In that case, the OPAE_PLATFORM_ROOT environment variable points to the hardware release, which defines the platform.
afu_sim_setup
is a wrapper for the following scripts. You can also access both of these scripts directly:
rtl_src_config
: This script transforms the list of RTL sources into simulator configuration files.generate_ase_environment.py
: This script instantiates your simulated platform configuration.
rtl_src_config¶
The /platforms/scripts/rtl_src_config
script maps a simple text file containing a list of RTL source files to an
ASE configuration file for simulation or an Intel Quartus Prime Pro configuration file for synthesis. rtl_src_config
also
defines preprocessor variables. Source configuration files may be hierarchical, with one file including another. rtl_src_config
can construct ASE-based simulation trees or Quartus build trees.
Run rtl_src_config --help
for a list of options and the required command syntax.
generate_ase_environment.py¶
The /ase/scripts/generate_ase_environment.py
generates platform configuration files. afu_sim_setup
invokes it
automatically. A legacy mode in generate_ase_environment.py
performs a brute-force check of the specified AFU RTL
directories, attempting to define a compilation. This brute-force mode is
imperfect and lists every file ending in .sv, .vs, .vhd, or .v
and directories separated by +
. It also may fail
when compilation is order-dependent.
Run generate_ase_environment.py --help
for a list of arguments.
The script requires a directory path to your RTL AFU.
-t
: The default for the optional-t
(tool) argument isVCS
. For Mentor tools, use theQUESTA
option.-p
: The default for the optional-p
(platform) argument isintg_xeon
which stands for the Integrated FPGA Platform. Usediscrete
for the Intel PAC.-x
: The optional exclusions argument lists exclusions for path searches.
The Synopsys and Mentor Graphics RTL simulators generate the following scripts.
Synopsys: Creates
synopsys_sim.setup
andvcs_run.tcl
in theVCS
configuration directory.Mentor Graphics: Creates
vsim_run.tcl
in theQUESTA
configuration directory.
The run-time simultation uses the .tcl
files.
Details on generated files:
vlog_files.list
: Lists all the Verilog and SystemVerilog files found in the AFU directory path.vhdl_files.list
: Lists all the VHDL files found in the AFU directory path.ase_sources.mk
: Ties the above two files intoDUT_VLOG_SRC_LIST
andDUT_VHD_SRC_LIST
Makefile variables.ASE_PLATFORM
: Sets the platform type to the default type or the type you specify.Set additional VCS or QUESTA options using the
SNPS_{VLOGAN,VHDLAN,VCS}_OPT
orMENT_{VLOG,VCOM,VSIM}_OPT
options in the Makefile. Refer to ASE Makefile Variables for more information.
The simulation files use absolute paths when possible. To improve portability across users and groups, substitute environment variables in the generated files that build and run the simulator.
Note
You must manually check this file for correctness before using it in the simulation.
Cleaning the ASE Environment¶
Use the ASE cleanup script located in scripts/ipc_clean.py
to kill zombie simulation processes and temporary files left
behind by failed simulation processes or crashes.
$ ./ase/scripts/ipc_clean.py
############################################################
# #
# ASE IPC Cleanup script #
# #
############################################################
IPC mounts seem to be readable... will attempt cleaning up IPC constructs by user ' user_foo '
Removing .ase_ready file ...
Type 'y' to clean up all zombie ase_simv processes : y
Going ahead with cleaning up ASE processes opened by user_foo
$
ASE Usage¶
The AFU ASE is a server-client simulation environment. The AFU RTL is the server process. The software application compiled and linked to the OPAE ASE library is the client process. Communication between server and client uses named pipes. The ASE abstracts most of the simulation infrastructure. You do not need to modify it.
Server Process:
The server process interfaces to 3rd-Party RTL Simulator packages. The server process currently supports Mentor Modelsim-SE* Questasim* and Synopsys CS-MX* via the SystemVerilog-DPI library and simulator software interface.
Named pipes implement communication to the client. Named pipes also implement control, status and session management. The server process includes a pipe event monitoring engine.
SystemVerilog manages the CCI-P interface. All CCI-P events are logged and time stamped.
The server also includes a CCI-P protocol checker that checks CCI-P transactions originating in the AFU. This checker identifies CCI-P protocol issues, hazards, race conditions, and so on.
The buffer allocation calls map to POSIX Shared Memory (
/dev/shm
). The server-client processes share information about these buffers using named pipes.
.. note::
The Physical addresses generated in ASE are not realistic and are not replicable in-system.
Client Process:
The client implements an OPAE interface and a library to access the ASE platform functionality including MMIO, Buffer management, and session control. The features available depend on the platform you specify at build time. These functions are available using the OPAE API.
The client process also provides a physical memory model that simulates the RTL AFU access to physical addresses. The physical memory model simulates address translation from virtual addresses to physical addresses.
A compiled program compiles and links to the ASE implementation of OPAE library. All OPAE calls route to ASE instead of the OPAE platform driver.
Separate build scripts build the server and client processes.
Server: A makefile in the
ase
directory compiles the ASE server process, containing the ASE Software, SystemVerilog engines and the AFU RTL logic code.Client: The main
cmake
script in the root of the distribution builds the OPAE library implementations for the System and ASE. The cmake script installs the library in thelib
directory.
AFU Build Instructions¶
ASE Application (Client) Build Instructions¶
Follow these instructions if you are building the OPAE SDK from a source tar file. Otherwise go directly to the Application build step.
Note
In these instructions, the directory /tmp/opae/
is the base directory where you install the OPAE API software
distribution. The /tmp
prefix may point to any system or user directory.
The ASE Source directory points to /tmp/opae/ase/
To build the OPAE libraries:
# Change directory to the opae directory
$ cd /tmp/opae/
# Check contents
$ ls
ase cmake common doc libopae platforms safe_string samples scripts tools AUTHORS CMakeLists.txt COPYING
README RELEASE_NOTES
# Create an out-of-build directory, and change to it
$ mkdir mybuild
$ cd mybuild
# Configure the software build using cmake (see options)
# $ cmake <Path to CMakeLists.txt>
# Install directory, in this example it is <Path to opae>/myinst/
$ cmake ../ -DOPAE_BUILD_SIM=YES -DCMAKE_INSTALL_PREFIX=/tmp/opae/myinst/
-- The C compiler identification is GNU 4.8.4
-- The CXX compiler identification is GNU 4.8.4
-- Check for working C compiler: /usr/bin/cc
-- Check for working C compiler: /usr/bin/cc -- works
.
.
.
-- Configuring done
-- Generating done
-- Build files have been written to: /tmp/opae/mybuild
# Build and install libraries
$ make
$ make install
# The environment Variable PATH should point to /myinst/bin
# Check library install paths
$ cd /tmp/opae/myinst/
$ ls
doc include lib
$ ls lib
libopae-c-ase.so libopae-c.so libopae-c.so.0 libopae-c.so.0.1.0 ...
Build the software application for the ASE using libopae-c-ase.so
and the gcc
command.
You can build the software application using one of the following three methods:
Dynamically Linking libopae-c-ase.so¶
# Change directory to <Path to Directory>/opae/samples/
# The UUID code requires the -luuid argument
# Linking to the ASE library requires the -lopae-c-ase argument
#
$ gcc -g -o hello_fpga hello_fpga.c -L /tmp/opae/myinst/lib/ -I /tmp/opae/myinst/include/ -luuid -lpthread -lopae-c-ase -std=c99
# When running the application be sure the relevant LD_LIBRARY_PATH variable is set
$ ./hello_fpga
Dynamically Linking to the System Library and then Overriding It¶
The ASE implementation of the OPAE library simulates system behavior. Consequently, the application may also link dynamically
to the System library, libopae-c.so
and libopae-c-ase.so
, and then override the system library with the
LD_PRELOAD
environment.
# Change directory to <Path to Directory>/opae/samples/
# The UUID code requires the -luuid argument
# Linking to the ASE library requires the -lopae-c-ase argument
#
$ gcc -g -o hello_fpga hello_fpga.c -L /tmp/opae/myinst/lib/ -I /tmp/opae/myinst/include/ -luuid -lpthread -lopae-c -std=c99
# When running the application be sure the relevant LD_LIBRARY_PATH variable is set
# You must also set the ASE_WORKDIR environment variable
$ LD_PRELOAD=libopae-c-ase.so ./hello_fpga
Compiling the libopae-c-ase.so Library with the OPAE Software Application¶
Use the OPAE ASE library implementation and compile it to the OPAE software application directly in one command using GCC.
# Compile command
$ gcc -g -o hello_fpga_ase hello_fpga.c /tmp/opae/myinst/lib/libopae-c-ase.so -I /tmp/opae/myinst/include/ -std=c99 -luuid
# When running the application, start the simulator, then set LD_LIBRARY_PATH and ASE_WORKDIR
$ ./hello_fpga_ase
ASE Simulator (Server) Build Instructions¶
ASE uses a platform differentiation key in the simulator Makefile to enable different platform features and produces a
simulator configuration based on the differentiation key. These keys are set automatically by afu_sim_setup
and
generate_ase_environment.py
.
You must note the following required build configurations:
| Configuration | Description | Default |
|:—————|:————|:——–|
| ASE_PLATFORM
| This is the platform differentiator. It must be set in ase_sources.mk
to point to the required simulator features. FPGA_PLATFORM_INTG_XEON
and FPGA_PLATFORM_DISCRETE
are the only legal values. | FPGA_PLATFORM_INTG_XEON
|
| SIMULATOR
| This must be set in ase_sources.mk
to point to the correct RTL simulator. VCS
and QUESTA
are the only legal values. | VCS
|
|DUT_VLOG_SRC_LIST
, DUT_VHDL_SRC_LIST
, and DUT_INCDIR
| These options point to AFU Verilog, VHDL and include path settings required for RTL simulators to build the simulation model correctly. | None supplied — You must specify this. |
For more information on other switches, refer to ASE Makefile targets
Use the scripts/generate_ase_environment.py
script to generate the AFU-specific files for the simulator build.
This script is not infallible and
requires manual inspection of generated configurations to achieve correct results.
Note
Edit ase_sources.mk to add AFU RTL-specific define macros or include paths.
You may use the Generate ASE Environment script to generate the required AFU ase_sources.mk
and vlog_files.list
files.
# change to ASE directory
$ cd /tmp/opae/ase/
# Use the scripts/generate_ase_environment.py
$ ./scripts/generate_ase_environment.py -t VCS -p discrete <Path to sample RTL>
.
.
.
# Edit files as needed.
$ ls
ase_sources.mk vcs_run.tcl synopsys_sim.setup vlog_files.list ...
You may need to check vlog_files.list
and ase_sources.mk
files for correctness. Now, build the simulator
with a ‘make’ command.
$ cd <opae>/ase/
$ make
.
.
$ ls work/ase_simv
work/ase_simv
ASE Runtime Instructions¶
The ASE server-client simulator makes the server before the client. Here are the run-time options:
$ make sim \
[SIMULATOR=<VCS|QUESTA>] \
[ASE_CONFIG=<Path to ase.cfg>] \
[ASE_SCRIPT=<Path to ase_regress.sh if ASE_MODE=4>]
Use two terminal windows to start the simulation.
Terminal 1: Runs
make sim
. The ASE initializes and the AFU issues a reset and then waits for incoming transactions. The software application must wait until the “Ready for Simulation” message displays.
Specify the environment variable ASE_WORKDIR
Terminal 1.
# Invoke the simulator
$ make sim
SIMULATOR=VCS
CC=gcc
#################################################################
# #
# OPAE Intel(R) Xeon(R) + FPGA Library #
# AFU Simulation Environment (ASE) #
# #
#################################################################
ASE platform set to MCP_SKYLAKE mode
.
.
.
SIM-SV: Transaction Logger started
SIM-SV: Simulator started...
SIM-C : +CONFIG /tmp/opae/ase/ase.cfg file found !
SIM-C : +SCRIPT /tmp/opae/ase/ase_regress.sh file found !
SIM-C : PID of simulator is 41819
SIM-C : Reading /tmp/opae/ase/ase.cfg configuration file
SIM-C : ASE was started in Mode 1 (Server-Client without SIMKILL)
ASE mode ... Server-Client mode without SIMKILL
Inactivity kill-switch ... DISABLED
Reuse simulation seed ... ENABLED
ASE Seed ... 1234
ASE Transaction view ... ENABLED
User Clock Frequency ... 312.500000 MHz, T_uclk = 3200 ps
Amount of physical memory ... 128 GB
.
.
.
SIM-C : ** ATTENTION : BEFORE running the software application **
Set env(ASE_WORKDIR) in the terminal where application will run (copy-and-paste) =>
$SHELL | Run:
---------|---------------------------------------------------
bash/zsh | export ASE_WORKDIR=/tmp/opae/ase/work
tcsh/csh | setenv ASE_WORKDIR /tmp/opae/ase/work
For any other $SHELL, consult your Linux administrator
SIM-C : Ready for simulation...
SIM-C : Press CTRL-C to close simulator...
You can close Terminal 1 make sim
by issuing a SIGTERM
to the relevant ase_simv
process or by typing CTRL-C
.
Terminal: First set the environment variable
ASE_WORKDIR
as specified in Terminal 1. In this exampleASE_WORKDIR
is set to/tmp/opae/ase/work
. Then, start the software application.
# Set ASE_WORKDIR environment variable
$ export ASE_WORKDIR=/tmp/opae/ase/work/
# Run the application
$ export LD_LIBRARY_PATH=/tmp/opae/myinst/lib/
$ LD_PRELOAD=libopae-c-ase.so ./hello_fpga
Note
After the application exits, the simulation is complete. Close the simulator to allow the waveform dump
process to complete. In Terminal 1, type the CTRL-C
command.
<Simulator running>
.
.
.
SIM-C : Ready to run next test
818602500C0Tx AlmFull toggled from 1 to 0
818602500C1Tx AlmFull toggled from 1 to 0
<CTRL-C Key hit>
^CSIM-C : Closing message queue and unlinking...
SIM-C : Unlinking Shared memory regions....
SIM-C : Session code file removed
SIM-C : Removing message queues and buffer handles ...
SIM-C : Cleaning session files...
SIM-C : Simulation generated log files
Transactions file | $ASE_WORKDIR/ccip_transactions.tsv
Workspaces info | $ASE_WORKDIR/workspace_info.log
ASE seed | $ASE_WORKDIR/ase_seed.txt
SIM-C : Tests run => 1
SIM-C : Sending kill command...

Transaction count | VA VL0 VH0 VH1 | MCL-1 MCL-2 MCL-4
========================================================================================
MMIOWrReq 9 |
MMIORdReq 2 |
MMIORdRsp 2 |
UMsgHint 0 |
UMsgData 0 |
RdReq 16384 | 0 0 16384 0 | 16384 0 0
RdResp 16384 | 0 0 16384 0 |
WrReq 16385 | 0 0 16385 0 | 16385 0 0
WrResp 16385 | 0 0 16385 0 | 16385 0 0
WrFence 1 | 0 0 1 0 |
WrFenRsp 1 | 0 0 1 0 |
$finish called from file "/tmp/opae/ase/rtl/ccip_emulator.sv", line 2657.
$finish at simulation time<PHONE_NUMBER>
V C S S i m u l a t i o n R e p o r t
Time:<PHONE_NUMBER> ps
CPU Time: 142.500 seconds; Data structure size: 1.1Mb
Tue Jun 20 13:29:13 2017
Upon completion, the simulation generates the following files:
Waveform dump:
make wave
opens the waveform for the selected tool.inter.vpd
: VCS Waveform filevsim.wlf
: Mentor/Questa waveform file.
$ASE_WORKDIR/ccip_transactions.tsv
: CCI-P Events log listing all events observed on the CCI-P interface. The timestamps indicate the corresponding time interval in the waveform dump VPD file.$ASE_WORKDIR/workspace_info.log
: Information about buffers the simulation opened.$ASE_WORKDIR/ase_seed.txt
: Information about the simulation seed.$ASE_WORKDIR/ccip_warnings_and_errors.txt
: Information about CCI-P warnings and errors.
Recommendations¶
The ASE
ccip_logger.sv
module logs CCI-P events for designs that use the CCI-P protocol. This module allows you to compare transactions and traffic flow through the CCI-P interfaces.
Note
Use a different file name for each instantiation of the of the ccip_logger
.
The ASE shutdowns simulations gracefully, closing all mutexes, locks, POSIX structures safely before exiting via the
$finish
statement in SystemVerilog. If your AFU design uses$error
or$finish
to identify error conditions while simulating, consider using the handlestart_simkill_countdown()
instead.start_simkill_countdown()
calls$finish
after completing the steps for a graceful shutdown.You can script ASE simulations. When the simulator is ready for use, the simulation writes a lock file,
$ASE_WORKDIR/.ase_ready
, to the work directory.
# Start Simulator in background
make sim &
# Wait for simulator readiness
# When .ase_ready is available in the $ASE_WORKDIR, the ASE is ready for simulation
while [ ! -f $ASE_WORKDIR/.ase_ready.pid ]
do
sleep 1
done
# Start application
cd $PATH_TO_APPLICATION
# Export ASE_WORKDIR variable
export ASE_WORKDIR={Path to simulator mentioned in ASE green printout}
./Application
To reduce simulation time, make the following changes to the default simulation settings:
Turn OFF wave dumps: Check your RTL vendor’s recommendation on switching off wave form dumps. In some cases, is possible to generate wave dumps for specific module hierarchies.
Turn OFF display messages by setting
ENABLE_CL_VIEW = 0
inase.cfg
.
To generate random CCI-P transactions for every run, modify the ASE latency model,
$ASE_SRCDIR/rtl/platform.vh
. The*_LATRANGE
constraint defines a min/max pair:
`define X_LATRANGE min, max
The min
and max
values are the minimum and maximum cycle counts for responses returning to the AFU. Simulation
assigns transactions a random latency in the (min, max) range. The larger the difference between (min, max), the larger the
standard deviation of latency for a given type of transaction. You can specify different (min, max) values for different
transaction types.
Note
The latency values specified for simulation are for testing only. They may not accurately represent the real latencies of your system hardware.
/*
* Latency model
* Coded as a Min,Max tuple
* -------------------------------------------------------
* RDLINE_LATRANGE : ReadLine turnaround time
* WRLINE_LATRANGE : WriteLine turnaround time
* UMSG_LATRANGE : UMsg latency
* INTR_LATRANGE : Interrupt turnaround time
*
* LAT_UNDEFINED : Undefined latency
*
*/
`define MMIO_LATENCY 15
`define RDLINE_S_LATRANGE 20,118
`define RDLINE_I_LATRANGE 20,118
`define WRLINE_M_LATRANGE 20,118
`define WRLINE_I_LATRANGE 20,118
`define UMSG_START2HINT_LATRANGE 39,41
`define UMSG_HINT2DATA_LATRANGE 41,45
`define UMSG_START2DATA_LATRANGE 82,85
`define INTR_LATRANGE 10,15
`define LAT_UNDEFINED 300
`define RDWR_VL_LATRANGE 20,118
`define RDWR_VH_LATRANGE 140,180
`define ASE_MAX_LATENCY 300
The ASE includes a CCI-P protocol checker,
$ASE_SRCDIR/rtl/ccip_checker.sv
. Use this module to verify CCI-P compliance. The checker sniffs transactions, conditions and header settings and flags warnings or errors. Identify multiple issue classes in thehw/ccip_sniffer.sv
. The ASE logs all warnings and errors in$ASE_WORKDIR/ccip_warnings_and_errors.txt
.
Memory errors in transactions: Memory errors have the highest severity. The simulation stops immediately. The ASE logs memory errors, including timestamps, in
$ASE_WORKDIR/ase_memory_error.log
.Protocol warnings: Warnings do not stop the simulation. The ASE logs warnings in
$ASE_WORKDIR/ccip_warning_and_errors.txt
.The ASE may also log memory hazards (RAW, WAR and WAW hazards).
ASE Example¶
A tutorial for CCI-P systems is available in a separate Basic Building Blocks repository
in the samples/tutorial tree. The first example,
01_hello_world follows the
afu_sim_setup
flow described above. Start with the tutorial’s
README file for configuration and execution
instructions. The example defines a set of sources and walks through the process of creating an ASE tree, running the
simulator and connecting it to a host program.
Operation Reference¶
ASE Simulator Makefile Switches¶
The ASE Makefile template comprises many targets and switches. Build your own compilation script for more complex simulations.
For a complete listing including the versions supported, see System Requirements section.
ASE Makefile Build Flow¶
Complete the following steps to compile ASE Simulator:
Compile Software objects of ASE into a library file *First compile the Software components located in the
ase/sw/
directory into a software library.
Note
Define SIM_SIDE
as a compilation macro when compiling the ASE simulator objects. The SIM_SIDE
switch is for simulation software, not the OPAE ASE software library.
Compile The ASE SystemVerilog files located in the
ase/rtl/
directory. Compile ASE RTL the platform components for the Integrated FPGA Platform or the Intel PAC into the simulation databases. For the PAC, compile the embedded memory interface (EMIF) Memory controller model into the ASE environment. If the simulation requires the Intel FPGA Gate libraries, compile the models into the ASE environment.Compile AFU components into the ASE environment. Use the RTL simulator software tools to compile the AFU components. Use Synopsys or Mentor utilities to compile VHDL or SystemVerilog components.
ASE Makefile Targets¶
| Target | Description |
|:——————-|:————|
| all
| Default build target, builds a simulator in Synopsys VCS-MX |
| header
| Print version and preamble |
| check
| Environment check |
| sw_build
| Build ase/sw/
components into a software library. The SIM_SIDE
switch builds the simulator software components |
| help
| Print help information |
| vcs_build
| Synopsys VCS-MX template build flow |
| questa_build
| Mentor Graphics Modelsim-SE/QuestaSim template build flow |
| sim
| Start the ASE Simulator |
| wave
| Open selected RTL waveform viewer |
| clean
| Clean build, simulation, and log files |
| distclean
| Clean distribution - removes the AFU configuration files |
ASE Makefile Variables¶
| Makefile target | Description | Default value |
|:——————-|:————|:————–|
| VCS_HOME
| Synopsys VCS-MX installation path | Installation tool specific |
| MTI_HOME
| Mentor installation path | Installation tool specific |
| QUARTUS_HOME
| Intel Quartus Prime Pro installation path | Installation tool specific |
| ASE_PLATFORM
| Platform selection switch:
Specify either tightly-coupled FPGA or programmable FPGA acceleration card using FPGA_PLATFORM_INTG_XEON
and FPGA_PLATFORM_DISCRETE
, respectively | FPGA_PLATFORM_INTG_XEON
|
| SIMULATOR
| Simulator Key to environment
Defined values VCS
or QUESTA
| VCS
|
| ASE_SRCDIR
| ASE source location | Current source path |
| ASE_WORKDIR
| Location where ASE runs, usually $ASE_SRCDIR/work
| Environment-specific execution path |
| WORK
| Simulation library compilation location | work
|
| ASE_DISABLE_LOGGER
| Switch to disable logger build | 0
|
| ASE_DISABLE_CHECKER
| Switch to disable checker build
WARNING: Disabling this checker may have side effects on protocol correctness | 0
|
| GLS_SIM
| Enable gate simulation build | 1
|
| GLS_VERILOG_OPT
| Libraries that enable Intel gate simulation | Quartus EDA simulation library paths|
| ASE_CONFIG
| ASE Run-time configuration file (described here) | $ASE_SRCDIR/ase.cfg
|
| ASE_SCRIPT
| ASE Regression script path | $ASE_SRCDIR/ase_regress.sh
|
| TIMESCALE
| Simulator timescale | 1ps/1ps
|
| ASEHW_FILE_LIST
| ASE RTL File list | Refer to ase/Makefile
|
| ASE_MEM_FILE_LIST
| ASE RTL file list for programmable FPGA acceleration card mode memory | Refer to ase/Makefile
|
| ASE_INCDIR
| ASE Include directory paths | Refer to ase/Makefile
|
| ASE_TOP
| ASE top level entity (must not be changed) | ase_top
|
| CC_OPT
| ASE Software Library compiler build options| -g -m64 -fPIC -D SIM_SIDE=1 -I $(ASE_SRCDIR)/sw/ -D SIMULATOR=VCS -D $(ASE_PLATFORM) -Wall -I $(VCS_HOME)/include/
|
| ASE_LD_SWITCHES
| ASE Software Linker switches | -lrt -lpthread -lstdc++ -luuid
|
| SNPS_VHDLAN_OPT
| Synopsys VCS-MX VHDL compile options (add extra options to ase_sources.mk
) | Refer to ase/Makefile
|
| SNPS_VLOGAN_OPT
| Synopsys VCS-MX SystemVerilog compile options (add extra options to ase_sources.mk
) | Refer to ase/Makefile
|
| SNPS_VCS_OPT
| Synopsys VCS-MX options for building simulator executable (add extra options to ase_sources.mk
) | Refer to ase/Makefile
|
| SNPS_SIM_OPT
| Synopsys VCS-MX Simulation options (add extra options may to ase_sources.mk
) | Refer to ase/Makefile
|
| MENT_VCOM_OPT
| Mentor Modelsim-SE/Questasim VHDL compile options (add extra options to ase_sources.mk
) | Refer to ase/Makefile
|
| MENT_VLOG_OPT
| Mentor Modelsim-SE/Questasim {System}Verilog compile options (add extra options to ase_sources.mk
) | Refer to ase/Makefile
|
| MENT_VSIM_OPT
| Mentor Modelsim-SE/Questasim VHDL simulation options (add extra options to ase_sources.mk
) | Refer to ase/Makefile
|
| DUT_VLOG_SRC_LIST
| Points to a text file listing AFU {System}Verilog files (usually vlog_files.list
) | User generated |
| DUT_VHDL_SRC_LIST
| Points to a text file listing AFU VHDL files (usually vhdl_files.list
| User generated |
| DUT_INCDIR
| Lists AFU include directories separated by a ‘+’ (usually in ase_sources.mk
) | User generated |
ASE Runtime Configuration Options¶
The ASE configuration file configures simulator behavior. An example configuration script is available at ase/ase.cfg
| Switch Name | Default | Description |
|:————————-|:———————————–|:————|
| ASE_MODE
| 1 | ASE mode has the following valid values:
1 : Standard Server-Client Mode
2 : Simulator stops after ASE_TIMEOUT
clocks
3 : Software shuts down simulator when client application releases session
4 : Regression mode invoked by script
>=5 : Ignored (revert to ASE_MODE=1
) |
| ASE_TIMEOUT
| 50000 (only if ASE_MODE=2
) | Watchdog timer shuts down simulator after ASE_TIMEOUT
clocks of CCI-P interface inactivity. |
| ASE_NUM_TESTS
| 500 (only if ASE_MODE=4
) | Number of tests in regression mode. If incorrectly set, the simulator may exit pre-maturely or stall waiting for tests to get started. |
| ENABLE_REUSE_D
| 1 | When set to 1, reuses the simulation seed, so that CCI-P transactions replay with the previous addresses.
When set to 0, obtains a new seed. |
| ASE_SEED
| 1234 (only if ENABLE_REUSE_SEED=1
) | ASE seed setting, enabled when ENABLE_REUSE_SEED
is set to 1, otherwise the simulations uses a different seed.
At the end of the simulation, the ASE writes the current seed to $ASE_WORKDIR/ase_seed.txt
. |
| ENABLE_CL_VIEW
| 1 | The ASE prints all CCI-P transactions. On long simulation runs, setting ENABLE_CL_VIEW
to 0 may reduce simulation time. |
| PHYS_MEMORY_AVAILABLE_GB
| 32 | Restricts ASE address generation the specified memory range. |
Logging Verbosity Control¶
ASE provides the following three levels for logging message verbosity. By default, these messages print to stdout
:
ASE_INFO: Prints mandatory information messages required to specify operation.
ASE_ERR: Prints error messages during operation.
ASE_MSG: Prints general messages indicating check points in the ASE. Suppress these messages by setting the environment variable
ASE_LOG
to0
.
The following command suppresses the ASE_MSG category:
$ ASE_LOG=0 LD_PRELOAD=libopae-c-ase ./hello_fpga
You cannot suppress warnings and errors.
Troubleshooting and Error Reference¶
The following list of ASE errors and warnings is not comprehensive:
| Observation | Problem | Next Steps |
|:————————–|:——————|:———————|
| Either all transactions are not seen or simulation ends earlier than expected. | ASE Simulation inactivity is too short for the application use-case to be successfully simulated in the ASE. | If using ASE_MODE=2
(Daemon with timeout), in the ase.cfg
file, increase the ASE_TIMEOUT
setting or disable ASE_TIMEOUT
. |
| ASE simulation build error - compilation, or linking failed | GCC version might be too old. | In the ase
directory try the following command
$ make sw_build
ASE builds correctly with GCC 4.8.5 or higher. Use the ase/scripts/env_check.sh
script to identify issues. |
| Synopsys VCS-MX dumped stack while compiling or running | Possible corruption of compiled objects or problems with incremental compilation. | Clean the ASE environment using $ make clean
If this command fails, clean the distribution with $ ./distclean.sh
then rebuild the simulation. |
| ERROR: Too many open files | Past ASE simulation runs did not close cleanly and may have left behind open IPC instances. | Use the $ASE_SRCDIR/scripts/ipc_clean.py
script to clean IPC instances.
Check if the System Requirements have been met.
If problems continue, increase resource limits for your Linux distribution. |
| $ASE_WORKDIR
environment variable has not been set up | Application cannot find a valid simulation session | Follow the steps printed when the ASE simulation starts. These instructions are in green text. |
| .ase_timestamp
cannot be opened at <DIRECTORY>
| Simulator may not have been started yet. Note that when started, the simulator prints:
Ready for Simulation$ASE_WORKDIR
may not set up correctly. | Check the ASE_WORKDIR environment variable. $ echo $ASE_WORKDIR
Wait for simulator to print:
Ready for Simulation
|
| ase_sources.mk: No such file or directory
| ASE Environment has not been generated. | Generate an AFU RTL listing (in vlog_files.list
and ase_sources.mk
) configuration.
You can use ase/scripts/generate_ase_environment.py
to generate these files. |
| An ASE instance is probably still running in current directory. | An ASE simulation is already running in the $ASE_WORKDIR
directory. | If the simulation process is unusable or unreachable, use the ase/scripts/ipc_clean.py
script to clean the simulation temporary files using: $ make clean
.
Then rebuild the simulator. |
Revision History¶
| Document Version | Intel Acceleration Stack Version | Changes |
| —————- |————————————|———-|
|2018.04.16 | 1.1 Alpha.
(Supported with Intel Quartus Prime Pro Edition 17.1.1.) | Made the following changes:
* Added afu_sim_setup
script which reads a file containing a list of RTL sources and constructs an ASE tree to compile and simulate.
* Added /platforms/scripts/rtl_src_config
script which maps a simple text file containing a list of RTL source files to an ASE configuration.
* Updated figures to show the hardware available in the Intel PAC with Arria® 10 GX FPGA. |


webview.cpp Example File
webenginewidgets/simplebrowser/webview.cpp/**************************************************************************** ** ** Copyright (C) 2016 The Qt Company Ltd. ** Contact: http://www.qt.io/licensing/ ** ** This file is part of the examples of the Qt Toolkit. ** ** $QT_BEGIN_LICENSE:BSD$ ** You may use this file under the terms of the BSD license as follows: ** ** "Redistribution and use in source and binary forms, with or without ** modification, are permitted provided that the following conditions are ** met: ** * Redistributions of source code must retain the above copyright ** notice, this list of conditions and the following disclaimer. ** * Redistributions in binary form must reproduce the above copyright ** notice, this list of conditions and the following disclaimer in ** the documentation and/or other materials provided with the ** distribution. ** * Neither the name of The Qt Company Ltd nor the names of its ** contributors may be used to endorse or promote products derived ** from this software without specific prior written permission.   ** ** $QT_END_LICENSE$ ** ****************************************************************************/ #include "browser.h" #include "browserwindow.h" #include "tabwidget.h" #include "webpage.h" #include "webpopupwindow.h" #include "webview.h" #include <QContextMenuEvent> #include <QDebug> #include <QMenu> #include <QMessageBox> #include <QTimer> WebView::WebView(QWidget *parent) : QWebEngineView(parent) , m_loadProgress(0) { connect(this, &QWebEngineView::loadProgress, [this](int progress) { m_loadProgress = progress; }); connect(this, &QWebEngineView::loadFinished, [this](bool success) { if (!success) { m_loadProgress = 0; } }); connect(this, &QWebEngineView::renderProcessTerminated, [this](QWebEnginePage::RenderProcessTerminationStatus termStatus, int statusCode) { QString status; switch (termStatus) { case QWebEnginePage::NormalTerminationStatus: status = tr("Render process normal exit"); break; case QWebEnginePage::AbnormalTerminationStatus: status = tr("Render process abnormal exit"); break; case QWebEnginePage::CrashedTerminationStatus: status = tr("Render process crashed"); break; case QWebEnginePage::KilledTerminationStatus: status = tr("Render process killed"); break; } QMessageBox::StandardButton btn = QMessageBox::question(window(), status, tr("Render process exited with code: %1\n" "Do you want to reload the page ?").arg(statusCode)); if (btn == QMessageBox::Yes) QTimer::singleShot(0, [this] { reload(); }); }); } void WebView::setPage(WebPage *page) { createWebActionTrigger(page,QWebEnginePage::Forward); createWebActionTrigger(page,QWebEnginePage::Back); createWebActionTrigger(page,QWebEnginePage::Reload); createWebActionTrigger(page,QWebEnginePage::Stop); QWebEngineView::setPage(page); } int WebView::loadProgress() const { return m_loadProgress; } void WebView::createWebActionTrigger(QWebEnginePage *page, QWebEnginePage::WebAction webAction) { QAction *action = page->action(webAction); connect(action, &QAction::changed, [this, action, webAction]{ emit webActionEnabledChanged(webAction, action->isEnabled()); }); } bool WebView::isWebActionEnabled(QWebEnginePage::WebAction webAction) const { return page()->action(webAction)->isEnabled(); } QWebEngineView *WebView::createWindow(QWebEnginePage::WebWindowType type) { switch (type) { case QWebEnginePage::WebBrowserTab: { BrowserWindow *mainWindow = qobject_cast<BrowserWindow*>(window()); return mainWindow->tabWidget()->createTab(); } case QWebEnginePage::WebBrowserBackgroundTab: { BrowserWindow *mainWindow = qobject_cast<BrowserWindow*>(window()); return mainWindow->tabWidget()->createTab(false); } case QWebEnginePage::WebBrowserWindow: { BrowserWindow *mainWindow = new BrowserWindow(); Browser::instance().addWindow(mainWindow); return mainWindow->currentTab(); } case QWebEnginePage::WebDialog: { WebPopupWindow *popup = new WebPopupWindow(page()->profile()); return popup->view(); } } return nullptr; } void WebView::contextMenuEvent(QContextMenuEvent *event) { QMenu *menu = page()->createStandardContextMenu(); const QList<QAction*> actions = menu->actions(); auto it = std::find(actions.cbegin(), actions.cend(), page()->action(QWebEnginePage::OpenLinkInThisWindow)); if (it != actions.cend()) { (*it)->setText(tr("Open Link in This Tab")); ++it; QAction *before(it == actions.cend() ? nullptr : *it); menu->insertAction(before, page()->action(QWebEnginePage::OpenLinkInNewWindow)); menu->insertAction(before, page()->action(QWebEnginePage::OpenLinkInNewTab)); } menu->popup(event->globalPos()); }


Logging into the app will initiate a sync of global and personal agenda data from the IBMtechU server (www.ibmtechu.com). This data will be stored locally to your device.
You may want to sync periodically, say once a day or if you have made a change to your agenda on the www.ibmtechu.com web application.
The Synchronization function pulls down two sets of information from the web application (ibmtechu.com) server.
When sessions are added to your personal agenda using this app, the sync operation does not sync these back upstream to the web application.
Surveys are automatically sent to the web application and are not part of the sync function.
Sessions can be added to your agenda plan using either the web application or this app. Sessions added with www.ibmtechu.com will appear with a white background vs a lightblue background using this app.
To download session materials, please log in to our www.ibmtechu.com server application.


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Add more houses as you update website


``
MEET THE TEAM
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 Stare at the wall, play with food and get confused by dust when in doubt, wash and meow all night having their mate disturbing sleeping humans pee in the shoe but attack dog, run away and pretend to be victim yet intrigued by the shower, for hide at bottom of staircase to trip human.
Chocolate gingerbread bear claw cookie. Bonbon jelly-o marzipan sweet biscuit. Candy tart chocolate pastry caramels fruitcake sesame snaps. Oat cake icing marzipan oat cake sugar plum tart oat cake tootsie roll. Souffle cake liquorice candy chocolate apple pie topping marzipan. Biscuit donut gummies pudding pastry. Sugar plum ice cream oat cake cake souffle sweet roll chocolate bar jelly. Croissant toffee lollipop. Biscuit wafer chocolate apple pie chocolate cake. Bear claw cotton candy chocolate cake gummies.
Croissant sugar plum oat cake gummi bears. Brownie sesame snaps lollipop muffin danish carrot cake marzipan halvah. Gingerbread apple pie gingerbread gummies cupcake. Candy canes pastry topping jelly-o dragee liquorice sweet. Carrot cake tiramisu candy gummies gummies lollipop donut chocolate cake. Halvah cotton candy tootsie roll tootsie roll biscuit chupa chups lollipop chocolate bar icing. Macaroon tiramisu fruitcake candy fruitcake sweet donut marzipan. Jelly beans bonbon dragee powder chocolate bar cookie. Souffle tart jelly beans candy canes.


I am
Dhruv Patel
from Gujrat, India. I'm doing B.tech programe in Mechanical engineering in Silver oak college of engineering and technology. In Mechanical engineering i 've special interest in Mechanics, Dynamics and Thermal.
Product Design is my area of work so far , i am also exploring in the areas of Digital manufacturing, Virtual prototyping, Programming and web Development.
Visit this
website to see
My background
Ahmedaabad is my home town. i completed my school studies in local school of Ahmedabad and now doing B.tech In Silver oak institute.
Previous work
Most of my work is in
- Product Design and development
- Structural Analysis
- Study of Fluid behavior


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{{ partial "header.html" . }} {{ .Title }} 404: Page Not Found. This is not the page you are looking. {{ partial "footer.html" . }}
404: Page Not Found. This is not the page you are looking.


Citing Visual Graphics Used:
The use of these images are for educational purposes only.
Google Images
Pinterest Images


---
layout: default
title: Skladačka
description: "Ihrisko - skladačka"
permalink: /sk/ihrisko/skladacka/
group: playground-project
parent: playground
lang: sk
language: Slovensky
thumbnail: playground-puzzle-2016-tile
order: 2
---
{% include image50vw.html basename="playground-puzzle-2016-02" alt="playground puzzle 2016" %}
{% include image50vw.html basename="playground-puzzle-2016-03" alt="playground puzzle 2016" %}
{% include image100vw.html basename="playground-puzzle-2016-01" alt="playground puzzle 2016" %}
Z núdze v daždivom počasí u babky sme našli pár farebných papierov a obliekali bábiku.
{% include playground-tiles.html %}


City Name:
Country Name:
The year you've visited:
Favorite Spot:
Record
Places visited:
City Name:
Country Name:
The Year Visited:
My Favorite Spot:


Scott Burns hacks on healthcare data at Stratasan. In a previous life, he developed large-scale neuroimaging infrastructure to study reading disabilities in children.


{{Infobox album |
| Name = Ascención
| Type = [[Album]]
| Artist = [[Malo]]
| Cover = malo_ascencion.jpg
| Border = yes
| Released = 1974
| Recorded = 1974
| Genre = [[Latin Rock]]
| Length = 41:13
| Label = [[Warner Bros. Records|Warner Bros.]]
| Producer = Fred Catero, [[Jorge Santana]], Pablo Tellez
| Reviews = * '''[[Allmusic]]''' {{Rating|2,5|5}}[{{Allmusic|class=album|id=r67329|pure_url=yes}} Link]
| Last album = ''[[Evolution (Malo album)|Evolution]]''
(1973)
| This album = '''''Ascención (Malo album)|Ascención'''''
(1974)
| Next album = ''[[Malo V]]''
(1981)
}}
'''''Ascención''''' is the fourth album by [[Latin Rock]] band [[Malo]], released in 1974.
== Track listing ==
# "Offerings" (Jorge Santana) - 5:40
# "A La Escuela" (Francisco Aquabella) - 3:15
# "Everlasting Night" (Jorge Santana/Bob Lazaneo) - 4:10
# "Latin Woman" (Ron Smith) - 4:05
# "Chevere" (Ron DeMasi/Pablo Tellez) - 3:58
# "Love Will Survive" (Ron DeMasi/Pablo Tellez) - 3:47
#"Think About Love" (Ron DeMasi) - 3:26
#"Tiempo de Recordar" (Pablo Tellez) - 3:17
#"Close to Me" (Ron DeMasi) - 2:40
#"No Matter" (Jorge Santana) - 6:55
#"Love Will Survive" (Single Version) (Ron DeMasi/Pablo Tellez) - 3:08
#"Think About Love" (Single Version) (Ron DeMasi) - 3:02
== Personnel ==
*Willy G (William Garcia): lead vocals
*Jorge Santana: guitar, percussion
*Francisco Aquabella: congas, bongos, timbales, lead vocal (on tracks 1 and 2)
*Tony Smith: drums, vocals
*Pablo Tellez: bass, timbales, percussion, vocals
*Ron DeMasi: organ, clavinet, electric piano, Mellotron, synthezier, vibes, vocals
*Steve Sherard: trombone
*Mike Fugate: trumpet
*Ron Smith: trumpet, Flugel horn
==Credits==
*Produced by Fred Catero, [[Jorge Santana]] and Pablo Tellez
*Recorded at Wally Heider Studio, San Francisco
*Chaos control: Douglas Tracy
*Recording and remix engineer: Fred Catero
*Synthesizer recorded at Different Fur Studio, San Francisco
*Engineer: John Vieira
*Art direction, design and photography: Rudy Rodriguez
*Cover art: Carlos Venegas and Eduardo Jaramillo
*Photography effects: George Rodriguez
==References==
*All information gathered from back cover of ''Ascención'' vinyl release ℗ 1974 [[Warner Bros. Records|Warner Bros.]], BS-2769
[[Discogs]] [[http://www.discogs.com/Malo-Ascenci%C3%B3n/release/2808073]]
==Charts==
'''Album''' - [[Billboard magazine|Billboard]] (US)
{| border=1 cellspacing=0 cellpadding=2 width="550px"
!align="left"|Year
!align="left"|Chart
!align="left"|Position
|-
|align="left"|1974
|align="left"|The Billboard 200
|align="left"|188
|-
|}
[[Category:1974 albums]]
[[Category:Malo albums]]
[[Category:Warner Bros. Records albums]]


|
DSL-ABM
|
#include "hsp_patient_transitions_tests.h"
Functions | |
| bool | test_susceptible_transitions () |
| Series of tests for transitions of a susceptible non-COVID hospital patient. More... | |
| bool | test_exposed_transitions () |
| Series of tests for transitions of an exposed non-COVID hospital patient. More... | |
| bool | test_symptomatic_transitions () |
| Series of tests for transitions of a symptomatic non-COVID hospital patient. More... | |
| ABM | create_abm (const double dt, int i0) |
| bool | check_values (std::vector< double > values) |
| Check if values in the vector meet logical criteria. More... | |
| bool | check_fractions (int num1, int num2, double fr_expected, std::string msg) |
| Check if num1/num2 is roughly equal to expected. More... | |
| bool | only_hospitals (const Agent &agent, const std::vector< Hospital > &hospitals, const std::vector< Household > &households, const std::vector< School > &schools, const std::vector< RetirementHome > &retirement_homes, const std::vector< Workplace > &workplaces) |
| Check if an agent is only registered in a hospital. More... | |
| bool | check_testing_transitions (const Agent &agent, const std::vector< Household > &households, const std::vector< Hospital > &hospitals, std::vector< int > &state_changes, int &n_tested_exposed, int &n_tested_sy, int &n_waiting_for_res, int &n_positive, int &n_false_neg, int &n_hsp, int &n_hsp_icu, int &n_ih, double time, double dt) |
| Tests for exposed agent that is undergoing testing or gets the results. More... | |
| bool | check_treatment_setup (const Agent &agent, const std::vector< Household > &households, const std::vector< Hospital > &hospitals, int &n_hsp, int &n_hsp_icu, int &n_ih, double time, double dt) |
| Verification of initial treatment. More... | |
| bool | check_symptomatic_agent_removal (const Agent &agent, const std::vector< Household > &households, const std::vector< Hospital > &hospitals, std::vector< int > &state_changes, int &n_rh, int &n_rd, double time, double dt) |
| Test for properties related to removal of a symptomatic agent. More... | |
| int | main () |
| bool check_fractions | ( | int | num1, |
| int | num2, | ||
| double | fr_expected, | ||
| std::string | msg | ||
| ) |
Check if num1/num2 is roughly equal to expected.
| bool check_symptomatic_agent_removal | ( | const Agent & | agent, |
| const std::vector< Household > & | households, | ||
| const std::vector< Hospital > & | hospitals, | ||
| std::vector< int > & | state_changes, | ||
| int & | n_rh, | ||
| int & | n_rd, | ||
| double | time, | ||
| double | dt | ||
| ) |
Test for properties related to removal of a symptomatic agent.
| bool check_testing_transitions | ( | const Agent & | agent, |
| const std::vector< Household > & | households, | ||
| const std::vector< Hospital > & | hospitals, | ||
| std::vector< int > & | state_changes, | ||
| int & | n_tested_exposed, | ||
| int & | n_tested_sy, | ||
| int & | n_waiting_for_res, | ||
| int & | n_positive, | ||
| int & | n_false_neg, | ||
| int & | n_hsp, | ||
| int & | n_hsp_icu, | ||
| int & | n_ih, | ||
| double | time, | ||
| double | dt | ||
| ) |
Tests for exposed agent that is undergoing testing or gets the results.
| bool check_treatment_setup | ( | const Agent & | agent, |
| const std::vector< Household > & | households, | ||
| const std::vector< Hospital > & | hospitals, | ||
| int & | n_hsp, | ||
| int & | n_hsp_icu, | ||
| int & | n_ih, | ||
| double | time, | ||
| double | dt | ||
| ) |
Verification of initial treatment.
| bool check_values | ( | std::vector< double > | values | ) |
Check if values in the vector meet logical criteria.
| ABM create_abm | ( | const double | dt, |
| int | i0 | ||
| ) |
| int main | ( | ) |
| bool only_hospitals | ( | const Agent & | agent, |
| const std::vector< Hospital > & | hospitals, | ||
| const std::vector< Household > & | households, | ||
| const std::vector< School > & | schools, | ||
| const std::vector< RetirementHome > & | retirement_homes, | ||
| const std::vector< Workplace > & | workplaces | ||
| ) |
Check if an agent is only registered in a hospital.
| bool test_exposed_transitions | ( | ) |
Series of tests for transitions of an exposed non-COVID hospital patient.
| bool test_susceptible_transitions | ( | ) |
Series of tests for transitions of a susceptible non-COVID hospital patient.
| bool test_symptomatic_transitions | ( | ) |
Series of tests for transitions of a symptomatic non-COVID hospital patient.


Warner, Labuschagne frustrate Pakistan in Adelaide
David Warner and Marnus Labuschagne pushed Australia to 70 for one after Pakistan made an early breakthrough before rain brought an early tea on the opening day of the second test at the Adelaide Oval on Friday.
MELBOURNE: David Warner and Marnus Labuschagne continued their torment of Pakistan's bowlers as they drove Australia to 139 for one at the dinner break on the opening day of the second test at Adelaide Oval on Friday.
Having each scored centuries in the first test win in Brisbane, the pair handled the pink ball superbly in their unbroken 131-run stand after they resumed following a long rain break after tea.
Warner was 72 not out, with Labuschagne on 60 at the break in the teams' first day-night match at the venue.
Pakistan's hopes of restricting Australia to a modest total bleakened in the twilight, as their re-jigged pace attack rarely threatened the batsmen's defences.
Azhar Ali's side also struggled in the field, with Warner's half-century secured with a touch of farce as he earned six runs when a wild throw at the stumps split the covering fielders and raced to the boundary.
Labuschagne brought up the sixth half-century of his blossoming test career with a sumptuous late cut for four off 19-year-old debutant paceman Muhammad Musa.
Seamer Shaheen Afridi had opener Joe Burns caught behind for four in the fourth over after Australian captain Tim Paine won the toss and chose to bat.
It was otherwise a barren afternoon for Pakistan, who were thrashed by an innings and five runs in the first test at the Gabba.
Musa received his first test cap from Pakistan great Wasim Akram before the start of play, having replaced 16-year-old prodigy Naseem Shah.
Imran Khan was also dropped in favour of more experienced quick Mohammad Abbas, who was surprisingly left out of the Brisbane test but did little early in Adelaide to reward the selectors' faith.
Top order batsman Imam-ul-Haq returned in place of Haris Sohail.
(Reporting by Ian Ransom; Editing by Richard Pullin, Muralikumar Anantharaman and Alex Richardson)


{% extends "layout_bsa.html" %} {% block page_title %} Prepay for NHS prescriptions {% endblock %} {% block content %} Prepay for NHS prescriptions Is the {{format}} holder's address the same as yours? Is the {{format}} holder's address the same as yours? Yes No Cancel {% endblock %}
Prepay for NHS prescriptions
Cancel


TABLE OF INTERACTIONS WITH
ANAGRELIDE
From the French ANSM drug interactions document of September 2016, p. 14
ANAGRELIDE RxNorm: 596724 ATC: L01XX35 |
ACETYLSALICYLIC ACID RxNorm: 1191 ATC: A01AD05 B01AC06 N02BA01 |
Increase of hemorrhagic events |
Not recommended |
ANAGRELIDE RxNorm: 596724 ATC: L01XX35 |
PLATELET AGGREGATION INHIBITORS CLASS CODE: B01AC-001 |
Increase of hemorraghic events |
Not recommended |
ANAGRELIDE RxNorm: 596724 ATC: L01XX35 |
MEDICATIONS THAT TEND TO INDUCE TORSADES DE POINTES CLASS CODE: C01-N05 |
Increased risk of ventricular arrhythmias, especially of torsades de pointes |
Precaution for use Clinical monitoring and EKG during the administration of these medications together. |


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Welcome to OpenEye, an application that allows you to see the various perspectives on today's news!
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| Emerging Stars |
Partners |
| Customer |
2015 RSV |
2020 RSV |
Trade Expenditure $m |
Other Resources $m |
Total $m |
% Total |
|
|
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|
|
|
|
| 0 |
0 |
0 |
0 |
0 |
0 |
0 |
| TOTAL |
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| Customer |
2015 RSV |
2020 RSV |
Trade Expenditure $m |
Other Resources $m |
Total $m |
% Total |
|
|
|
|
|
|
|
| 0 |
0 |
0 |
0 |
0 |
0 |
0 |
| TOTAL |
|
|
|
|
|
|
|
| Niche Players |
Scale |
| Customer |
2015 RSV |
2020 RSV |
Trade Expenditure $m |
Other Resources $m |
Total $m |
% Total |
|
|
|
|
|
|
|
| 0 |
0 |
0 |
0 |
0 |
0 |
0 |
| TOTAL |
|
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|
|
|
| Customer |
2015 RSV |
2020 RSV |
Trade Expenditure $m |
Other Resources $m |
Total $m |
% Total |
|
|
|
|
|
|
|
| 0 |
0 |
0 |
0 |
0 |
0 |
0 |
| TOTAL |
|
|
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|
|
|
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| Other |
| Customer |
2015 RSV |
2020 RSV |
Trade Expenditure $m |
Other Resources $m |
Total $m |
% Total |
| Total Other |
|
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|
|
|
| TOTAL |
|
|
|
|
|
|
|
| Total |
| Customer |
2015 RSV |
2020 RSV |
Trade Expenditure $m |
Other Resources $m |
Total $m |
% Total |
| TOTAL |
|
|
|
|
|
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|


| Currently studying Internet Technologies on ICT College of Vocational Studies, second year in Belgrade. Finished High School of Machinery & Electrotech, "Goša" in home city. I'm a gamer in my free time, and therefore an idea for this year website. :) | ||
| First and last name: Bogdan Matorkić | E-Mail<EMAIL_ADDRESS>| |
| Date of birth: 12.9.1992 | Facebook: bogdan.coldstein | |
| Place of birth: Smederevska Palanka | Twitter: 43.Guitar.God |


So far we have assumed that all the regressors have been independent from each other. That is to say, that the value of regressor #1 does not affect the value of regressor #2. In real life, is this always the case? Suppose we are modelling the sales of an ice-cream vendor. We are regressing Sales against Weather and Temperature. Can we claim that the current weather has no effect on the temperature? No, we cannot!
This is where the interaction term comes into play. Assume that bad weather has a value of 0, while good weather has a value of 1. We can model this regression with $${Sales = a*Weather + b*Temperature + c*(Weather*Temperature)}$$ Mathematically, this causes the coefficient of temperature to change depending on the weather. In other words, the current weather will determine the effect of temperature on sales. (Or vice versa). If this confuses you, have no fear! We will go into actual numerical analysis in the coding section below.
Let us take a look at the following dataset.
ols = smf.ols(formula='Sales ~ TV + Radio + Newspaper', data=df)
result = ols.fit()
print(result.summary())
Notice how this model predicts a unit change in TV advertisements increases sales by 0.0458, and a unit change in Radio advertisements increases sales by 0.1885? Let's add in an interaction term between TV and Radio now. You can specify an interaction term with the statsmodels package with the ":" symbol.
ols = smf.ols(formula='Sales ~ TV + Radio + Newspaper + TV:Radio', data=df)
result = ols.fit()
print(result.summary())
The coefficients for the variables seemed to have drastically changed! Compare Radio's coefficient now, and in the previous model! It has dropped from 0.1885 to 0.0280! The interaction term between TV and Radio comes in at 0.0011. What does this mean?
A unit change in Radio advertisements causes the effectiveness of TV's advertisements to increase (Or vice versa)! The p-value of the interaction term is also < 0.05, and the R-squared value of the model also rises from 0.897 to 0.968! This is almost a 70% increase in remaining variance that is now explained by the new and superior model!
It turns out that a lot of Radio's effect on sales is actually indirectly caused by Radio's effect on TV!
Interaction terms can occur with anything. When performing a regression analysis, it is advisable to use logic and intuition to figure out if some of your chosen variables might interact with each other, and create multiple models to check your assumptions.
Student is a boolean variable, with 0 indicating that they are not a student, and 1 indicating that they are. Given everything else is constant, how much would a unit change in rating affect balance when:
a) The person is not a student?
b) The person is a student?
Done with the exercises? Simple, weren't they? The next section will be on a new model type, Next Page the probit and logit regression!


Tanjung Piai by-election: Vote in the morning, thunderstorm risk in the evening
PONTIAN, Nov 15 — Voters in the Tanjung Piai parliamentary by-election are advised to go to the polls in the morning following the risk of thunderstorms tomorrow evening.
National Weather and Geophysics Operations Centre of the Malaysian Meteorological Department (MetMalaysia) in a statement today predicted the weather in the morning would be sunny with temperatures between 23 and 25 degrees Celsius, while in the afternoon thunderstorms with temperatures between 25 and 28 degrees Celsius was expected.
A total of 52,471 registered voters in Tanjung Piai will carry out their responsibilities by turning up to vote tomorrow.
The Tanjung Piai by-election was being held following the death of incumbent Datuk Dr Md Farid Md Rafik, 42, of Pakatan Harapan (PH) on September 21 due to heart complications.
The by-election will witness a six-cornered fight involving PH candidate Karmaine Sardini against BN, Gerakan, Parti Barisan Jemaah Islamiah (Berjasa) and two independent candidates. — Bernama


Google, Facebook business incompatible with privacy rights, says Amnesty International
by BNNHuman rights organisation Amnesty International has found in a study that the «surveillance-based business model» of Facebook and Google’s is incompatible with the right to privacy. The U.S. companies disagree.
German public broadcaster Deutsche Welle reports on Thursday, November 21, that Amnesty International in a report has said tech giants Facebook and Google should be forced to abandon what it calls a «surveillance-based business model» that is «predicated on human rights abuse.»
«Despite the real value of the services they provide, Google and Facebook’s platforms come at a systemic cost,» the human rights group said in its 60-page report this week.
Amnesty believes that by gathering up personal data to feed advertising businesses, the two firms carry out an unprecedented assault on privacy rights.
Amnesty said that by gathering up personal data to feed advertising businesses, the two firms carry out an unprecedented assault on privacy rights.
U.S. firms disagree
Facebook disagreed with the report’s findings. Steve Satterfield, the company’s public policy director, rejected the notion that the business model was «surveillance-based» and noted that users sign up voluntarily for the service.
Google also disputed Amnesty’s findings, DW reports.


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This page displays measures for the network Semantic Network [Behavioral2 x Situational].
Network images have nodes colored by group and sized by betweenness centrality.
Behavioral2-Level Measures
These measures were run on the specified network, and produced a vector of values, one value for each Behavioral2 node.
Input network: Semantic Network [Behavioral2 x Situational]
Measure Min Mean Max Std.Dev Centrality, Hub 0.692 0.846 1 0.154 Centrality, Hub [Unscaled] 0.569 0.696 0.822 0.127 Centrality, Out-Degree 0.061 0.075 0.089 0.014 Centrality, Out-Degree [Unscaled] 56 68.500 81 12.500 Situational-Level Measures
These measures were run on the specified network, and produced a vector of values, one value for each Situational node.
Input network: Semantic Network [Behavioral2 x Situational]
Measure Min Mean Max Std.Dev Centrality, Authority 0 0.029 0.329 0.080 Centrality, Authority [Unscaled] 0 0.021 0.233 0.057 Centrality, In-Degree 0 0.075 0.844 0.206 Centrality, In-Degree [Unscaled] 0 7.211 81 19.739 Overall Top-Ranked Behavioral2
This chart shows the Behavioral2 nodes that are top-ranked overall using the node-level measures listed below. The value shown for a node is the average of its measure values, each of which is first converted into a z-score. The final scores are then normalized to be between zero and one.
There are 2 nodes in the nodeset.
Overall Score Measure List
Centrality, Hub [Semantic Network [Behavioral2 x Situational]]
Centrality, Out-Degree [Semantic Network [Behavioral2 x Situational]]
Centrality, Hub
A node is hub-central to the extent that its out-links are to nodes that have many in-links. Individuals or organizations that act as hubs are sending information to a wide range of others each of whom has many others reporting to them. Technically, an agent is hub-central if its out-links are to agents that have many other agents sending links to them. The scientific name of this measure is hub centrality and it is calculated on agent by agent matrices.
If the node of interest has a higher than normal value (greater than 1 standard deviation(s) above the mean) the row is colored red. The row is green if the node is within 1 standard deviation of the mean. Finally, the row is colored blue if the node has a lower than normal value (less than one standard deviation(s) below the mean).
Input network(s): Semantic Network [Behavioral2 x Situational]
Rank Behavioral2 Value Unscaled 1 simplifying 1 0.822 2 judging 0.692 0.569
Value statistics Min: 0.692 Mean: 0.846 Lower quartile: 0.692 Max: 1 Std.dev: 0.154 Median: 0.846 Upper quartile: 1
Unscaled value statistics Min: 0.569 Mean: 0.696 Lower quartile: 0.569 Max: 0.822 Std.dev: 0.127 Median: 0.696 Upper quartile: 0.822 Centrality, Out-Degree
For any node, e.g. an individual or a resource, the out-links are the connections that the node of interest has to other nodes. For example, imagine an agent by knowledge network where the number of out-links an agent would have is the number of pieces of knowledge it is connected to. The scientific name of this measure is out-degree and it can be calculated on any network.
If the node of interest has a higher than normal value (greater than 1 standard deviation(s) above the mean) the row is colored red. The row is green if the node is within 1 standard deviation of the mean. Finally, the row is colored blue if the node has a lower than normal value (less than one standard deviation(s) below the mean).
Input network(s): Semantic Network [Behavioral2 x Situational]
Rank Behavioral2 Value Unscaled 1 simplifying 0.089 81 2 judging 0.061 56
Value statistics Min: 0.061 Mean: 0.075 Lower quartile: 0.061 Max: 0.089 Std.dev: 0.014 Median: 0.075 Upper quartile: 0.089
Unscaled value statistics Min: 56 Mean: 68.500 Lower quartile: 56 Max: 81 Std.dev: 12.500 Median: 68.500 Upper quartile: 81 Overall Top-Ranked Situational
This chart shows the Situational nodes that are top-ranked overall using the node-level measures listed below. The value shown for a node is the average of its measure values, each of which is first converted into a z-score. The final scores are then normalized to be between zero and one.
There are 19 nodes in the nodeset.
Overall Score Measure List
Centrality, Authority [Semantic Network [Behavioral2 x Situational]]
Centrality, In-Degree [Semantic Network [Behavioral2 x Situational]]
Centrality, Authority
A node is authority-central to the extent that its in-links are from nodes that have many out-links. Individuals or organizations that act as authorities are receiving information from a wide range of others each of whom sends information to a large number of others.
If the node of interest has a higher than normal value (greater than 1 standard deviation(s) above the mean) the row is colored red. The row is green if the node is within 1 standard deviation of the mean. Finally, the row is colored blue if the node has a lower than normal value (less than one standard deviation(s) below the mean).
Input network(s): Semantic Network [Behavioral2 x Situational]
Rank Situational Value Unscaled 1 impact 0.329 0.233 2 vulnerabilities 0.166 0.118 3 opportunity_for_criminal_acts 0.049 0.034 4 trap 0.008 0.006 5 parent-child_experience 0.005 0.003 6 alarm 0 0 7 commercial 0 0 8 crime 0 0 9 days 0 0 10 deployment 0 0 11 free 0 0 12 harm 0 0 13 investigation 0 0 14 party 0 0 15 social 0 0 16 sponsored 0 0 17 supervised 0 0 18 technical 0 0 19 war 0 0
Value statistics Min: 0 Mean: 0.029 Lower quartile: 0 Max: 0.329 Std.dev: 0.080 Median: 0 Upper quartile: 0.005
Unscaled value statistics Min: 0 Mean: 0.021 Lower quartile: 0 Max: 0.233 Std.dev: 0.057 Median: 0 Upper quartile: 0.003 Centrality, In-Degree
The number of links directed into a node normalized by the maximum number of such links. This measure is also called Column Degree Centrality because it is computed by taking the sum of the column values in the input network.
If the node of interest has a higher than normal value (greater than 1 standard deviation(s) above the mean) the row is colored red. The row is green if the node is within 1 standard deviation of the mean. Finally, the row is colored blue if the node has a lower than normal value (less than one standard deviation(s) below the mean).
Input network(s): Semantic Network [Behavioral2 x Situational]
Rank Situational Value Unscaled 1 impact 0.844 81 2 vulnerabilities 0.427 41 3 opportunity_for_criminal_acts 0.125 12 4 trap 0.021 2 5 parent-child_experience 0.010 1 6 alarm 0 0 7 commercial 0 0 8 crime 0 0 9 days 0 0 10 deployment 0 0 11 free 0 0 12 harm 0 0 13 investigation 0 0 14 party 0 0 15 social 0 0 16 sponsored 0 0 17 supervised 0 0 18 technical 0 0 19 war 0 0
Value statistics Min: 0 Mean: 0.075 Lower quartile: 0 Max: 0.844 Std.dev: 0.206 Median: 0 Upper quartile: 0.010
Unscaled value statistics Min: 0 Mean: 7.211 Lower quartile: 0 Max: 81 Std.dev: 19.739 Median: 0 Upper quartile: 1


src/app/app-routing.module.ts
import { NgModule } from "@angular/core";
import { Routes, RouterModule } from "@angular/router";
import { HomeComponent } from "./components/home";
import { LoginComponent } from "./components/login";
import { UserProfileComponent } from "./components/user-profile/user-profile.component";
import { SignupComponent } from "./components/signup/signup.component";
import { AuthGuard } from "./shared/auth.guard";
import { DishSearchComponent } from "./components/customer/dish-search";
import { AgmCoreModule } from "@agm/core";
import { DishSearchModule } from "./components/customer/dish-search";
import {
OrderHistoryComponent,
OrderHistoryModule,
} from "./components/customer/order-history";
import { CreateOrderComponent } from "./components/customer/create-order";
import { CreateOrderModule } from "./components/customer/create-order";
import {
OrderDetailsComponent,
OrderDetailsModule,
} from "./components/customer/order-details";
import { PartnerDishesComponent } from "./components/partner/partner-dishes/partner-dishes.component";
import { PartnerDishesModule } from "./components/partner/partner-dishes/partner-dishes.module";
import { AddDishModule } from "./components/partner/add-dish";
import { AddDishComponent } from "./components/partner/add-dish/add-dish.component";
import { PartnerDashboardComponent } from "./components/partner/partner-dashboard/partner-dashboard.component";
import { PartnerDashboardModule } from "./components/partner/partner-dashboard/partner-dashboard.module";
import { EditDishComponent } from "./components/partner/edit-dish/edit-dish.component";
import { EditDishModule } from "./components/partner/edit-dish/edit-dish.module";
import { ChatFormComponent } from "./components/chat-form/chat-form.component";
import {
AdminCustomerComponent,
AdminCustomerModule,
} from "./components/admin/admin-customer";
import {
AdminPartnersComponent,
AdminPartnersModule,
} from "./components/admin/admin-partners";
import { AdminPartnerComponent } from "./components/admin/admin-partner";
import { AdminPartnerDishesComponent } from "./components/admin/admin-partner-dishes";
import { AdminDashboardComponent } from "./components/admin/admin-dashboard";
import { MessageOfflineComponent } from "./components/message-offline";
const routes: Routes = [
{ path: "login", component: LoginComponent },
{ path: "home", component: HomeComponent },
{ path: "signup", component: SignupComponent },
{
path: "userprofile/:id",
component: UserProfileComponent,
canActivate: [AuthGuard],
},
{ path: "search", component: DishSearchComponent },
{ path: "history", component: OrderHistoryComponent },
{ path: "order/:id", component: CreateOrderComponent },
{ path: "orders/:id", component: OrderDetailsComponent },
{ path: "partner/dashboard", component: PartnerDashboardComponent },
{ path: "partner/dishes", component: PartnerDishesComponent },
{ path: "partner/addDish", component: AddDishComponent },
{ path: "partner/editDish/:id", component: EditDishComponent },
{ path: "admin/customerDashboard", component: AdminCustomerComponent },
{ path: "admin/partnerDashboard", component: AdminPartnersComponent },
{ path: "admin/partner/:id/orders", component: AdminPartnerComponent },
{ path: "admin/partner/:id/dishes", component: AdminPartnerDishesComponent },
{ path: "contactus", component: ChatFormComponent },
{ path: "admin/dashboard", component: AdminDashboardComponent },
{ path: "message", component: MessageOfflineComponent },
{ path: "**", component: HomeComponent },
];
@NgModule({
imports: [
RouterModule.forRoot(routes),
AgmCoreModule.forRoot({
apiKey: "AIzaSyAp53JpK3NUmD_7Sv5mMp5ElN4P6XLy1OE",
libraries: ["places"],
}),
],
exports: [
RouterModule,
DishSearchModule,
OrderHistoryModule,
CreateOrderModule,
OrderDetailsModule,
PartnerDishesModule,
AddDishModule,
PartnerDashboardModule,
EditDishModule,
AdminPartnersModule,
AdminCustomerModule,
],
})
export class AppRoutingModule {}


06/08/2020
Here's some stuff before the code
# this is not a title inline code block **mamma mia marcello**
other stuff after the code with some inline code
Just a couple more things to add to the markdown compiler.
=====
and ------
for titles and subtitles[image alt text][number of image in an index]
for images and linksI'm thinkng of some modifications I could make to Markdown, like embedding youtube videos and stuff, but what we already have is enough for a simple blog such as this one.
Maybe in the future I could also move away from new.css and use my own CSS rules. There's no objective need for it, but there's also no objective need for yet another static site generator.


Condoms recalled in Uganda over quality concerns
by AFPGlobal health charity Marie Stopes said Wednesday it had recalled hundreds of thousands of faulty condoms on sale in Uganda, where HIV rates are among the highest in the world.
The recall followed a warning from Uganda’s National Drug Authority (NDA) that the Life Guard brand condoms had failed to manufacture “quality tests” because they contained holes and may burst.
The affected condoms were manufactured by India-based MHL Healthcare in April 2019 and have an expiry date of April 2024, the government regulator said.
Marie Stopes Uganda spokesman David Kamu told AFP on Wednesday that the two affected batches each contained “around 400,000” condoms.
Earlier reports had suggested millions of condoms could have been involved but NDA spokesman Fred Ssekyana told AFP the figure was below one million.
Marie Stopes Uganda said more than half of the condoms of concern had been recalled.
“While the LifeGuard brand follows strict quality controls, unfortunately, two recent batches have fallen short of the quality we demand,” the charity’s country director, Carole Sekimpi, said in a statement Tuesday.
Marie Stopes is the largest and most specialised sexual reproductive health organisation in Uganda, the charity says on its website.
According to UNAIDS, 1.4 million Ugandans are living with HIV.
Last year 53,000 people were newly infected with the disease in the East African country, the UN agency said.